MT90823AL1 ZARLINK [Zarlink Semiconductor Inc], MT90823AL1 Datasheet - Page 17

• Manufacturer Part Number: MT90823AL1
• Description: 3V Large Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

15-10
1 - 0
9-5
Bit
DR1
4
3
2
0
0
1
1
15
0
Read/Write Address:
Reset Value:
BPD4-0
Unused
14
DR1-0
Name
0
OSB
BPE
SFE
DR0
0
1
0
1
13
0
Table 9 - Serial Data Rate Selection (16 input x 16 output)
12
Must be zero for normal operation.
Block Programming Data. These bits carry the value to be loaded into the
connection memory block whenever the memory block programming feature is
activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to
1, the contents of the bits BPD4- 0 are loaded into bit 15 to bit 11 of the connection
memory. Bit 10 to bit 0 of the connection memory are set to 0.
Begin Block programming Enable. A zero to one transition of this bit enables the
memory block programming function. The BPE and BPD4-0 bits in the IMS register
have to be defined in the same write operation. Once the BPE bit is set high, the
device requires two frames to complete the block programming. After the
programming function has finished, the BPE bit returns to zero to indicate the
operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort
the programming operation.
When BPE = 1, the other bits in the IMS register must not be changed for two frames
to ensure proper operation.
Output standby. When ODE = 0 and OSB = 0, the output drivers of STo0 to STo15
are in high impedance mode. When ODE = 0 and OSB = 1, the output driver of STo0
to STo15 function normally. When ODE = 1, STo0 to STo15 output drivers function
normally.
Start Frame Evaluation. A zero to one transition in this bit starts the frame evaluation
procedure. When the CFE bit in the FAR register changes from zero to one, the
evaluation procedure stops. To start another frame evaluation cycle, set this bit to
zero for at least one frame.
Data Rate Select. Input/Output data rate selection. See Table 9 for detailed
programming.
0
Table 8 - Interface Mode Selection (IMS) Register Bits
11
0
01
0000
Data Rate Selected
H
10
,
0
H
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
.
Reserved
BPD
4
Zarlink Semiconductor Inc.
9
MT90823
BPD
8
3
17
BPD
7
2
Description
BPD
6
1
BPD
5
0
BPE
4
Master Clock Required
OSB
3
16.384 MHz
4.096 MHz
8.192 MHz
Reserved
SFE
2
DR1
1
Data Sheet
DR0
0