MT90823AL1 ZARLINK [Zarlink Semiconductor Inc], MT90823AL1 Datasheet - Page 15

• Manufacturer Part Number: MT90823AL1
• Description: 3V Large Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

If the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of
the frame delay offset registers must be set to zero.
Notes:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
2. Channels 0 to 31 are used when serial interface is at 2Mb/s mode.
3. Channels 0 to 63 are used when serial interface is at 4Mb/s mode.
4. Channels 0 to 127 are used when serial interface is at 8Mb/s mode.
(Note 1)
OE bit in Connection
A7
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Memory
A6
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
A5
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
.
Table 4 - Internal Register and Address Memory Mapping
A4
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
.
.
.
Don’t Care
ODE pin
Table 5 - Output High Impedance Control
0
0
1
A3
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
.
.
.
A2
Zarlink Semiconductor Inc.
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
.
.
.
OSB bit in IMS register
MT90823
A1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
15
.
.
.
Don’t Care
Don’t care
0
1
A0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
.
.
.
Control Register, CR
Interface Mode Selection Register, IMS
Frame Alignment Register, FAR
Frame Input Offset Register 0, FOR0
Frame Input Offset Register 1, FOR1
Frame Input Offset Register 2, FOR2
Frame Input Offset Register 3, FOR3
Ch 0
Ch 1
.
Ch 30
Ch 31
Ch 32
Ch 33
.
Ch 62
Ch 63
Ch 64
Ch 65
.
Ch 126
Ch 127
ST-BUS Output Driver Status
High Impedance
High Impedance
Location
Per Channel
Enable
Enable
Data Sheet
(Note 2)
(Note 3)
(Note 4)