AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 166

• Manufacturer Part Number: AM79C970AKCW
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: AMD [Advanced Micro Devices]

TMD0
Bit
31–0 TBADR
TMD1
Bit
31
30
29 ADD_FCS/NO
166
_FCS
AMD
ADD_FCS
Name
Name
OWN
ERR
Description
Transmit Buffer address. This
field contains the address of the
transmit buffer that is associated
with this descriptor.
Description
This bit indicates whether the
descriptor entry is owned by
the host (OWN = 0) or
the
(OWN = 1). The host sets the
OWN bit after filling the buffer
pointed to by the descriptor entry.
The PCnet-PCI II controller
clears the OWN bit after transmit-
ting the contents of the buffer.
Both the PCnet-PCI II controller
and the host must not alter a de-
scriptor entry after it has relin-
quished ownership.
ERR is the OR of UFLO, LCOL,
LCAR, RTRY or BPE. ERR is set
by the PCnet-PCI II controller
and cleared by the host. This bit
is set in the current descriptor
when the error occurs, and there-
fore may be set in any descriptor
of a chained buffer transmission.
Bit
SWSTYLE (BCR20, bits 7–0) is
set
Otherwise bit 29 functions as
ADD_FCS.
ADD_FCS dynamically controls
the generation of FCS on a
frame by frame basis. It is valid
only if the STP bit is set. When
ADD_FCS is set, the state of
DXMTFCS
transmitter FCS generation is
activated. When ADD_FCS is
cleared
generation
DXMTFCS. When APAD_XMT
(CSR4, bit 11) is set to ONE,
the setting of ADD_FCS has no
effect. ADD_FCS is set by
the host, and is not changed
by the PCnet-PCI II controller.
This
the C-LANCE (Am79C90). This
function differs from the corre-
sponding ILACC function.
29
PCnet-PCI
to ONE
is
functions
a
to
is
is
reserved
ZERO,
(ILACC style).
controlled
ignored
II
as
controller
P R E L I M I N A R Y
bit
when
FCS
Am79C970A
and
by
by
in
28 MORE/LTINT
27
NO_FCS
MORE
LTINT
ONE
NO_FCS dynamically controls
the generation of FCS on a frame
by frame basis. It is valid only if
the ENP bit is set. When
NO_FCS is set, the state of
DXMTFCS is ignored and trans-
mitter FCS generation is deacti-
vated. When NO_FCS is cleared
to ZERO, FCS generation is con-
trolled by DXMTFCS. When
APAD_XMT (CSR4, bit 11) is set
to ONE, the setting of NO_FCS
has no effect. NO_FCS is set by
the host, and is not changed by
the PCnet-PCI II controller. This
is a reserved bit in the C-LANCE
(Am79C90). This function is
identical to the corresponding
ILACC function.
Bit 28 always function as MORE.
The value of MORE is written by
the PCnet-PCI II controller and is
read by the host. When LTINTEN
is cleared to ZERO (CSR5, bit
14), the PCnet-PCI II controller
will never look at the content of bit
28, write operations by the host
have no effect. When LTINTEN
is set to ONE bit 28 changes its
function to LTINT on host write
operations and on PCnet-PCI II
controller read operations.
MORE indicates that more than
one retry was needed to transmit
a frame. The value of MORE is
written by the PCnet-PCI II con-
troller. This bit has meaning only
if the ENP bit is set.
LTINT is used to suppress inter-
rupts after successful transmis-
sion on selected frames. When
LTINT is cleared to ZERO and
ENP
PCnet-PCI II controller will not
set TINT (CSR0, bit 9) after a
successful transmission. TINT
will only be set when the last de-
scriptor of a frame has both
LTINT and ENP set to ONE.
When LTINT is cleared to ZERO,
it will only cause the suppression
of interrupts for successful trans-
mission. TINT will always be set if
the transmission has an error.
The LTINTEN overrides the func-
tion of TOKINTD (CSR5, bit 15).
ONE indicates that exactly one
retry was needed to transmit a
frame. ONE flag is not valid when
is
set
to
ONE,
the