AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 75

• Manufacturer Part Number: AM79C970AKCW
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: AMD [Advanced Micro Devices]

If a collision is detected after 512 bit times have been
transmitted, the collision is termed a late collision. The
MAC Engine will abort the transmission, append the jam
sequence and set the LCOL bit. No retry attempt will be
scheduled on detection of a late collision, and the trans-
mit message will be flushed from the FIFO.
The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires
use of a “truncated binary exponential backoff”
algorithm which provides a controlled pseudo random
mechanism to enforce the collision backoff interval, be-
fore re-transmission is attempted.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
“At the end of enforcing a collision (jamming), the
CSMA/CD sublayer delays before attempting to re-
transmit the frame. The delay is an integer multiple of
slot Time. The number of slot times to delay before the
nth re-transmission attempt is chosen as a uniformly
distributed random integer r in the range:
where
The PCnet-PCI II controller provides an alternative algo-
rithm, which suspends the counting of the slot time/IPG
during the time that receive carrier sense is detected.
This aids in networks where large numbers of nodes are
present, and numerous nodes can be in collision. It ef-
fectively accelerates the increase in the backoff time in
busy networks, and allows nodes not involved in the col-
lision to access the channel whilst the colliding nodes
await a reduction in channel activity. Once channel ac-
tivity is reduced, the nodes resolving the collision time
out their slot time counters as normal.
This modified backoff algorithm is enabled when EMBA
(CSR3, bit 3) is set to ONE.
TRANSMIT OPERATION
The transmit operation and features of the PCnet-PCI II
controller are controlled by programmable options. The
PCnet-PCI II controller offers a 272-byte transmit FIFO
to provide frame buffering for increased system latency,
automatic re-transmission with no FIFO reload, and
automatic transmit padding.
Transmit Function Programming
Automatic transmit features such as retry on collision,
FCS generation/transmission, and pad field insertion
can all be programmed to provide flexibility in the
(re-)transmission of messages.
Disable retry on collision (DRTY) is controlled by the
DRTY bit of the Mode register (CSR15) in the
initialization block.
Automatic pad field insertion is controlled by the
0
k = min (n,10).”
r <2k
P R E L I M I N A R Y
Am79C970A
APAD_XMT bit in CSR4.
The disable FCS generation/transmission feature can
be programmed as a static feature or dynamically on a
frame by frame basis.
Transmit FIFO Watermark (XMTFW) in CSR80 sets the
point at which the BMU requests more data from the
transmit buffers for the FIFO. A minimum of XMTFW
empty spaces must be available in the transmit FIFO be-
fore the BMU will request the system bus in order to
transfer transmit frame data into the transmit FIFO.
Transmit Start Point (XMTSP) in CSR80 sets the point
when the transmitter actually attempts to transmit a
frame onto the media. A minimum of XMTSP bytes must
be written to the transmit FIFO for the current frame be-
fore transmission of the current frame will begin. (When
automatically padded packets are being sent, it is con-
ceivable that the XMTSP is not reached when all of the
data has been transferred to the FIFO. In this case, the
transmission will begin when all of the frame data has
been placed into the transmit FIFO.) The default value of
XMTSP is 01b, meaning there has to be 64 bytes in the
transmit FIFO to start a transmission.
Automatic Pad Generation
Transmit frames can be automatically padded to extend
them to 64 data bytes (excluding preamble). This allows
the minimum frame size of 64 bytes (512 bits) for
802.3/Ethernet to be guaranteed with no software inter-
vention from the host/controlling process. Setting the
APAD_XMT bit in CSR4 enables the automatic padding
feature. The pad is placed between the LLC data field
and FCS field in the 802.3 frame. FCS is always added if
the frame is padded, regardless of the state of
DXMTFCS (CSR15, bit 3) or ADD_FCS/NO_FCS
(TMD1, bit 29). The transmit frame will be padded by
bytes with the value of 00h. The default value of
APAD_XMT is 0, which will disable automatic pad gen-
eration after H_RESET.
It is the responsibility of upper layer software to correctly
define the actual length field contained in the message
to correspond to the total number of LLC Data bytes en-
capsulated in the frame (length field as defined in the
ISO 8802-3 (IEEE/ANSI 802.3) standard). The length
value contained in the message is not used by the
PCnet-PCI II controller to compute the actual number of
pad bytes to be inserted. The PCnet-PCI II controller will
append pad bytes dependent on the actual number of
bits transmitted onto the network. Once the last data
byte of the frame has completed, prior to appending the
FCS, the PCnet-PCI II controller will check to ensure
that 544 bits have been transmitted. If not, pad bytes are
added to extend the frame size to this value, and the
FCS is then added.
AMD
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