S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 117

• Manufacturer Part Number: S71WS256NC0BAWE32
• Description: Stacked Multi-Chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

26 Low Power Features
26.7 Partial Array Refresh (PAR) mode
26.8 Driver Strength Optimization
26.1
September 15, 2005 S71WS-N_01_A4
Internal TCSR
The PAR mode enables the user to specify the active memory array size. This device consists of
4 blocks and the user can select 1 block, 2 blocks, 3 blocks or all blocks as active memory arrays
through the Mode Register Setting. The active memory array is periodically refreshed whereas
the disabled array is not refreshed, so the previously stored data is lost. Even though PAR mode
is enabled through the Mode Register Setting, PAR mode execution by the MRS# pin is still
needed.
The normal operation can be executed even in refresh-disabled array as long as the MRS# pin is
not driven to the Low condition for over 0.5 µs. Driving the MRS# pin to the High condition puts
the device back to the normal operation mode from the PAR executed mode. Refer to
and
Notes:
1.
2.
The optimization of output driver strength is possible through the mode register setting to adjust
for the different data loadings. Through this driver strength optimization, the device can minimize
the noise generated on the data bus during read operation. The device supports full drive, 1/2
drive and 1/4 drive.
The internal Temperature Compensated Self Refresh (TCSR) feature is a very useful tool for re-
ducing standby current at room temperature (below 40°C). DRAM cells have weak refresh
characteristics in higher temperatures. High temperatures require more refresh cycles, which can
lead to standby current increase.
Without the internal TCSR, the refresh cycle should be set at worst condition so as to cover the
high temperature (85°C) refresh characteristics. But with internal TCSR, a refresh cycle below
40°C can be optimized, so the standby current at room temperature can be greatly reduced. This
feature is beneficial since most mobile phones are used at or below 40°C in the phone standby
mode.
Partial Refresh(3/4 Block)
Partial Refresh(1/2 Block)
Partial Refresh(1/4 Block)
Only the data in the refreshed block are valid.
The PAR Array can be selected through Mode Register Set (see
Standby (Full Array)
Table 26.1
Power Mode
A d v a n c e
for PAR operation and PAR address mapping.
MODE
000000h ~ 3FFFFFh
000000h ~ 2FFFFFh
000000h ~ 1FFFFFh
000000h ~ 0FFFFFh
MRS#
CS#
Figure 26.1 PAR Mode Execution and Exit
(Bottom Array)
I n f o r m a t i o n
Table 26.1 PAR Mode Characteristics
(Note
Address
S71WS-Nx0 Based MCPs
Normal
Operation
2)
Suspend
0.5 µs
000000h ~ 3FFFFFh
100000h ~ 3FFFFFh
200000h ~ 3FFFFFh
300000h ~ 3FFFFFh
(Top Array)
(Note
Address
PAR mode
2)
Mode Register Setting
Valid
Memory Cell
Data
(Note
Normal
Operation
1)
Operation).
Standby Current
(µA, Max)
TBD
TBD
TBD
TBD
Figure 26.1
Wait Time
(µs)
0
115