S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 156
S71WS256NC0BAWE32
Manufacturer Part Number
S71WS256NC0BAWE32
Description
Stacked Multi-Chip Product (MCP)
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71WS256NC0BAWE32.pdf
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41 Synchronous Burst Operation Terminology
41.1
41.2
41.3
154
Clock (CLK)
Latency Count
Burst Length
Clock
ADV#
Address
Data out
Data out
Data out
Data out
The clock input is used as the reference for synchronous burst read and write operation of the
pSRAM. The synchronous burst read and write operations are synchronized to the rising edge of
the clock. The clock transitions must swing between V
The Latency Count configuration tells the device how many clocks must elapse from the burst
command before the first data should be available on its data pins. This value depends on the
input clock frequency.
Note:
WAIT# pin.
Burst Length identifies how many data the device outputs during an access. The device supports
4 word, 8 word, 16 word and 256 word burst read or write. 256 word Full page burst mode needs
to meet t
The first data will be output with the set Latency + t
output with t
The first data will always keep the Latency. From the second data on, some period of wait time may be caused by
Clock Frequency
Latency Count
# of Clocks for 1st data (Write)
BC
# of Clocks for 1st data (Read)
(Burst Cycle time) parameter as 2500ns max.
CD
T
from each clock.
Set Latency
Latency 3
Latency 4
Latency 5
Latency 6
Table 41.1
Table 41.2 Number of CLocks for 1st Data
Figure 41.1 Latency Configuration (Read)
A d v a n c e
S71WS-Nx0 Based MCPs
Table 41.1 Latency Count Support
Up to 66 MHz
shows the supported Latency Count.
5
DQ1
I n f o r m a t i o n
DQ2
DQ1
Latency 3
CD
4
2
DQ3
DQ2
DQ1
. From the second data on, the data will be
IL
Up to 54 MHz
and V
DQ4
DQ3
DQ1
DQ2
4
IH
.
DQ5
DQ4
DQ2
DQ3
Latency 4
5
3
DQ6
DQ4
DQ3
DQ5
S71WS-N_01_A4 September 15, 2005
DQ7
DQ5
DQ4
DQ6
Up to 40 MHz
Latency 5
3
DQ8
DQ7
DQ6
DQ5
6
4
DQ8
DQ9
DQ7
DQ6
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