S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 29

• Manufacturer Part Number: S71WS256NC0BAWE32
• Description: Stacked Multi-Chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

10.3
September 15, 2005 S71WS-N_01_A4
Synchronous (Burst) Read Mode & Configuration Register
When a series of adjacent addresses needs to be read from the device (in order from lowest to
highest address), the synchronous (or burst read) mode can be used to significantly reduce the
overall time needed for the device to output array data. After an initial access time required for
the data from the first address location, subsequent data is output synchronized to a clock input
provided by the system.
The device offers both continuous and linear methods of burst read operation, which are dis-
cussed in subsections
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the
configuration register must be set to enable the burst read mode. Other Configuration Register
settings include the number of wait states to insert before the initial word (t
access, the burst mode in which to operate, and when RDY indicates data is ready to be read.
Prior to entering the burst mode, the system should first determine the configuration register set-
tings (and read the current register settings if desired via the Read Configuration Register
command sequence), and then write the configuration register command sequence. See
10.3.7,
The device outputs the initial word subject to the following operational conditions:
The device outputs subsequent words t
which also increments the internal address counter. The device outputs burst data at this rate sub-
ject to the following operational conditions:
t
latched to valid data on the device outputs.
configuration register setting CR13–CR11: the total number of clock cycles (wait states)
that occur before valid data appears on the device outputs. The effect is that t
lengthened.
IACC
Configuration
specification: the time from the rising edge of the first clock cycle after addresses are
A d v a n c e
Configuration Register
Synchronous Mode
Figure 10.1 Synchronous/Asynchronous State Diagram
Set Burst Mode
Command for
(CR15 = 0)
Register, and
10.3.4
I n f o r m a t i o n
S71WS-Nx0 Based MCPs
and 10.3.5, and 10.3.6.
Asynchronous Read
Synchronous Read
Hardware Reset
Power-up/
Mode Only
Mode Only
Table
BACC
Configuration Register
15.1,
Asynchronous Mode
after the active edge of each successive clock cycle,
Set Burst Mode
Command for
(CR15 = 1)
Memory Array Commands
for further details.
IACC
) of each burst
IACC
Section
is
27