S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 89
S71WS256NC0BAWE32
Manufacturer Part Number
S71WS256NC0BAWE32
Description
Stacked Multi-Chip Product (MCP)
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71WS256NC0BAWE32.pdf
(188 pages)
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A d v a n c e
I n f o r m a t i o n
Data
D0
D1
Rising edge of next clock cycle
AVD#
following last wait state triggers
next burst data
total number of clock cycles
following addresses being latched
OE#
1
2
3
4
5
6
7
CLK
4
5
0
1
2
3
number of clock cycles
programmed
Wait State Configuration Register Setup:
D13, D12, D11 = “111” ⇒ Reserved
D13, D12, D11 = “110” ⇒ Reserved
D13, D12, D11 = “101” ⇒ 5 programmed, 7 total
D13, D12, D11 = “100” ⇒ 4 programmed, 6 total
D13, D12, D11 = “011” ⇒ 3 programmed, 5 total
Note: Figure assumes address D0 is not at an address boundary, and wait state is set to “101”.
Figure 14.23 Example of Wait States Insertion
September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
87
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