AM41LV3204MB10IT AMD [Advanced Micro Devices], AM41LV3204MB10IT Datasheet - Page 59

• Manufacturer Part Number: AM41LV3204MB10IT
• Description: Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM
• Manufacturer: AMD [Advanced Micro Devices]

AC CHARACTERISTICS
Notes:
1. CE1#s controlled.
2. t
3. t
4. t
5. A write occurs during the overlap (t
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asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
to the end of write.
CW
WR
AS
Address
CE1#s
CE2s
UB#s, LB#s
WE#
Data In
Data Out
is measured from the address valid to the beginning of write.
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
Figure 29. SRAM Write Cycle—CE1#s Control
WP
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
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P R E L I M I N A R Y
t
AS
(See Note 2 )
Am41LV3204M
WR
(See Note 3)
applied in case a write ends as CE1#s or WE# going high.
t
t
AW
CW
t
(See Note 5)
WC
t
BW
t
WP
t
DW
Data Valid
WP
is measured from the beginning of write
t
WR
t
DH
(See Note 4)
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June 10, 2003