K4T1G084QD SAMSUNG [Samsung semiconductor], K4T1G084QD Datasheet - Page 27

• Manufacturer Part Number: K4T1G084QD
• Description: 1Gb D-die DDR2 SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

K4T1G084QD
K4T1G164QD
29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
30. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
31. Input waveform timing is referenced from the input signal crossing at the V
32. Input waveform timing is referenced from the input signal crossing at the V
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the
35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the
36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
of tIS + 2*tCK + tIH.
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between Vil(dc)max and Vih(dc)min.
single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the
single-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between Vil(dc)max and Vih(dc)min.
time it takes to achieve the 3 clocks of registeration. Thus, after any cKE transition, CKE may not transitioin from its valid level during the time period
tial data strobe crosspoint for a rising signal, and from the input signal crossing at the V
signal applied to the device under test.
tial data strobe crosspoint for a rising signal and V
device under test.
device under test.
DQS
DQS
CK
CK
< Differential Input waveform timing >
tDS
IL(dc)
tIS
to the differential data strobe crosspoint for a falling signal applied to the device under test.
tDH
tIH
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IH(ac)
IL(dc)
tDS
level for a rising signal and V
level for a rising signal and V
tIS
tDH
IL(ac)
tIH
level to the differential data strobe crosspoint for a falling
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
IH(dc)
IL(ac)
max
max
min
min
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
Rev. 1.0 March 2007
for a falling signal applied to the
for a falling signal applied to the
DDR2 SDRAM
max
max
min
min
IH(ac)
IH(dc)
level to the differen-
level to the differen-