PPC440EPX-NPAFFFTS AMCC [Applied Micro Circuits Corporation], PPC440EPX-NPAFFFTS Datasheet - Page 14

• Manufacturer Part Number: PPC440EPX-NPAFFFTS
• Description: PowerPC 440EPx Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

440EPx – PPC440EPx Embedded Processor
DDR2/1 SDRAM Memory Controller
The Double Data Rate 2/1 (DDR2/1) SDRAM memory controller supports industry standard discrete devices that
are compatible with both the DDR1 or DDR2 specifications. The correct I/O supply voltage must be provided for the
two types of DDR devices: DDR1 devices require +2.5 V and DDR2 devices require +1.8 V.
Global memory timings, address and bank sizes, and memory addressing modes are programmable.
Features include:
External Peripheral Bus Controller (EBC)
Features include:
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• PCI Power Management 1.1
• PCI register set addressable both from on-chip processor and PCI device sides
• Ability to boot from PCI bus memory
• Error tracking/status
• Supports initiation of transfers of the following types:
• 32-bit memory interface for DDR1
• 32- or 64-bit memory interface for DDR2
• Optional Error Checking and Correcting (ECC)
• 2.6-GB/s peak data rate
• Two memory banks of up to 1 GB each
• Maximum capacity of 2GB
• Support for 128-Mb, 256-Mb, 512-Mb, and 1-Gb DDR devices, with CAS latencies of 2, 2.5, or 3
• Clock frequencies from 133 MHz (266 Mbps) to 166 MHz (333 Mbps) supported
• Page mode accesses (up to 16 open pages) with configurable paging policy
• Programmable address mapping and timing
• Software initiated self-refresh
• Power management (self-refresh, suspend, sleep)
• One or two chip selects
• Up to six ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
• Up to 83 MHz operation
• Burst and non-burst devices
• 32-bit byte-addressable data bus
• Data parity
• 30-bit address
• Peripheral Device pacing with external “Ready”
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device
• Programmable address mapping
• External DMA Slave Support
(Faster parts may be used, but must be clocked no faster than 166 MHz)
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
– 256 Wait States for non-burst
– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
– Programmable CSon, CSoff relative to address
– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
Revision 1.26 – October 15, 2007
Preliminary Data Sheet
AMCC Proprietary