PPC440EPX-NPAFFFTS AMCC [Applied Micro Circuits Corporation], PPC440EPX-NPAFFFTS Datasheet - Page 55
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PPC440EPX-NPAFFFTS
Manufacturer Part Number
PPC440EPX-NPAFFFTS
Description
PowerPC 440EPx Embedded Processor
Manufacturer
AMCC [Applied Micro Circuits Corporation]
Datasheet
1.PPC440EPX-NPAFFFTS.pdf
(94 pages)
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Revision 1.26 – October 15, 2007
Signal Descriptions
The PPC440EPx embedded controller is packaged in a 680-ball thermally enhanced plastic ball grid array
(TE-PBGA). The following tables describe the package level pin-out.
In the table Table 8 on page 57, each I/O signal is listed along with a short description of its function. Active-low
signals (for example, RAS) are marked with an overline. Please see Table 5 on page 21 for the pin (ball) number to
which each signal is assigned.
Multiplexed Signals
Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases,
the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same
pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in Table 5
on page 21. It is expected that in any single application a particular pin will always be programmed to serve the
same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise
be possible.
Note: Signals multiplexed with GPIO default to GPIO receivers and float after reset. Initialization software must
configure the GPIO registers for the desired function as described in the GPIO chapter of the user’s manual. Any of
these signals requiring a particular state prior to running initialization code must be terminated with pull ups or pull
downs.
Multipurpose Signals
In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address
pins (PerAddr) are used as outputs by the PPC440EPx to broadcast an address to external slave devices when the
PPC440EPx has control of the external bus. When, during normal operation, an external master gains ownership
AMCC Proprietary
Preliminary Data Sheet
Table 7. Pin Summary
Total Signal Pins
Total Power Pins
Total Pins
Reserved
EAGND
UAGND
Group
SOV
EOV
EAV
UAV
AGND
AV
OV
GND
V
DD
DD
DD
DD
DD
DD
DD
440EPx – PPC440EPx Embedded Processor
No. of Pins
367
192
313
680
26
14
12
56
1
1
1
1
4
5
0
55
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