PPC440EPX-NPAFFFTS AMCC [Applied Micro Circuits Corporation], PPC440EPX-NPAFFFTS Datasheet - Page 6

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PPC440EPX-NPAFFFTS

Manufacturer Part Number
PPC440EPX-NPAFFFTS
Description
PowerPC 440EPx Embedded Processor
Manufacturer
AMCC [Applied Micro Circuits Corporation]
Datasheet
440EPx – PPC440EPx Embedded Processor
Block Diagram
Figure 2. PPC440EPx Functional Block Diagram
The PPC440EPx is a system on a chip (SOC) using IBM CoreConnect Bus
Address Maps
The PPC440EPx incorporates two address maps. The first is a fixed processor System Memory Address Map.
This address map defines the possible contents of various address regions which the processor can access. The
second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software
running on the PPC440EPx processor through the use of mtdcr and mfdcr instructions.
6
333MHz max
data rate
- 14-bit addr
- 64/32-bit data
Interrupts
External
UIC
FPU
10
(optional)
Security
Controller
DDR2/1
SDRAM
Control,
Reset
Clock
Controller
D-Cache
PLB (PLB4—128 bits)
DMA
32KB
JTAG
OPB 1
Device
Processor
PPC440
USB 2.0
Timers
MMU
2.0 PHY
Bridge
OPB
D+/D−
I-Cache
Host
32KB
Trace
Power
Bridge
Mgmt
OPB
OPB 2
SRAM
16KB
Bridge
OPB
MAL
DCR Bus
DCRs
PLB-PLB
Bridges
10/100/1000
ZMII
Ethernet
83MHz max
x2
- 30-bit addr
- 32/16-bit data
RGMII
On-chip Peripheral Bus (OPB 0)
Peripheral
Controller
External
Bridge
GPIO
OPB
PLB (PLB3—64 bits)
Architecture.
Revision 1.26 – October 15, 2007
Preliminary Data Sheet
SPI
Controller
NAND
Controller
Flash
DMA
IIC
x2
Bridge
PCI
BSC
GPT
66MHz max
- 32 bits
- 6 devices
AMCC Proprietary
UART
x4

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