PPC440EPX-NPAFFFTS AMCC [Applied Micro Circuits Corporation], PPC440EPX-NPAFFFTS Datasheet - Page 58

no-image

PPC440EPX-NPAFFFTS

Manufacturer Part Number
PPC440EPX-NPAFFFTS
Description
PowerPC 440EPx Embedded Processor
Manufacturer
AMCC [Applied Micro Circuits Corporation]
Datasheet
440EPx – PPC440EPx Embedded Processor
Table 8. Signal Functional Description (Sheet 2 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3 kΩ to OV
3. Must pull down (recommended value is 1 kΩ)
4. If not used, must pull up (recommended value is 3 kΩ to OV
5. If not used, must pull down (recommended value is 1 kΩ)
6. Strapping input during reset; pull-up or pull-down required
58
DDR2/1 SDRAM Interface
BA0:2
BankSel0:1
CAS
ClkEn
DM0:7
DM8
DQS0:7
DQS8
ECC0:7
MemAddr00:13
MemData00:63
MemClkOut
MemClkOut
MemODT0:1
RAS
WE
S
S
VREF1A:B
VREF2A:B
Signal Name
Bank Address supporting up to eight internal banks.
Selects up to two external DDR SDRAM banks.
Column Address Strobe.
Clock Enable.
Memory write data byte lane masks. DM8 is the byte lane mask
for the ECC byte lane.
Byte lane data strobe.
Byte lane data strobe for ECC.
ECC check bits 0:7.
Memory address bus.
Memory data bus (MemData32:63 available for DDR2 only).
Subsystem clock.
DDR2 On-die termination enable (not used with DDR1).
Row Address Strobe.
Write Enable.
DDR SDRAM reference voltage 1 input.
DDR SDRAM reference voltage 2 input.
DD
(EOV
Description
DD
DD
for Ethernet)
(EOV
DD
for Ethernet)
Revision 1.26 – October 15, 2007
Preliminary Data Sheet
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
I
I
Volt ref receiver
(1.25 V or 0.9 V )
(1.25 V or 0.9 V )
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
Volt ref driver
2.5 V (1.8 V)
2.5 V (1.8 V)
2.5 V (1.8 V)
2.5 V (1.8 V)
2.5 V (1.8 V)
2.5 V (1.8 V)
2.5 V (1.8 V)
2.5 V (1.8 V)
2.5 V (1.8 V)
2.5 V (1.8 V)
2.5 V (1.8 V)
2.5 V (1.8 V)
2.5 V (1.8 V)
Diff driver
Type
AMCC Proprietary
Notes

Related parts for PPC440EPX-NPAFFFTS