EDD5108AFTA_06 ELPIDA [Elpida Memory], EDD5108AFTA_06 Datasheet - Page 14

• Manufacturer Part Number: EDD5108AFTA_06
• Description: 512M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point
of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point
of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the
VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock
input to this pin. The other input signals are referred at CK rising edge.
/CS (input pin)
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0
to the A9, and A11 at the cross point of the CK rising edge and the /CK falling edge in a read or a write command
cycle. This column address becomes the starting address of a burst operation.
[Address Pins Table]
Part number
EDD5108AFTA
EDD5116AFTA
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = high when read or write
command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.
BA0 and BA1 (input pins)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)
[Bank Select Signal Table]
Bank 0
Bank 1
Bank 2
Bank 3
Remark: H: VIH. L: VIL.
Data Sheet E0699E50 (Ver. 5.0)
Address (A0 to A12)
Row address
AX0 to AX12
AX0 to AX12
H
BA0
L
H
L
14
EDD5108AFTA, EDD5116AFTA
Column address
AY0 to AY9, AY11
AY0 to AY9
BA1
L
L
H
H