EDD5108AFTA_06 ELPIDA [Elpida Memory], EDD5108AFTA_06 Datasheet - Page 31

• Manufacturer Part Number: EDD5108AFTA_06
• Description: 512M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Command Intervals
A Read command to the consecutive Read command Interval
1. Same
2. Same
3. Different
Data Sheet E0699E50 (Ver. 5.0)
Command
Destination row of the
consecutive read command
Bank
address
Address
DQS
/CK
DQ
CK
BA
Bank0
Active
Row address State
Same
Different
Any
ACT
Row
t0
READ to READ Command Interval (same ROW address in the same bank)
NOP
ACTIVE
—
ACTIVE
IDLE
Column A
READ
t4
Operation
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank without interrupting the preceding read operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive read command can be issued.
Column = A
Read
Column B
READ
t5
Column = B
Read
31
t6
EDD5108AFTA, EDD5116AFTA
t7
Column = A
Dout
out
A0
out
A1
NOP
t8
out
B0
Column = B
Dout
out
B1
t9
out
B2
out
B3
t10
CL = 3
BL = 4
Bank0
t11