H5TQ4G43AMR HYNIX [Hynix Semiconductor], H5TQ4G43AMR Datasheet - Page 16

• Manufacturer Part Number: H5TQ4G43AMR
• Description: 4Gb DDR3 SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 1.0 / Dec. 2009
(optional)
Symbol
I
I
I
I
I
DDQ4R
I
DD4W
DD4R
DD3P
DD5B
DD6
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8
Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open;
Output Buffer and RTT: Enabled in Mode Registers
Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst
with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer
and RTT: Enabled in Mode Registers
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst
with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output
Buffer and RTT: Enabled in Mode Registers
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8
mand, Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM:
stable at 0; Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in
Mode Registers
Self-Refresh Current: Normal Temperature Range
T
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8
Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Out-
put Buffer and RTT: Enabled in Mode Registers
CASE
: 0 - 85
o
C; Auto Self-Refresh (ASR): Disabled
b)
; ODT Signal: stable at 0; Pattern Details: see Table 9.
b)
; ODT Signal: stable at 0; Pattern Details: see Table 7.
b)
; ODT Signal: stable at HIGH; Pattern Details: see Table 8.
Description
b)
; ODT Signal: MID_LEVEL
b)
d)
; ODT Signal: stable at 0
;Self-Refresh Temperature Range (SRT): Normal
a)
a)
a)
; AL: 0; CS: stable at 1; Command, Address,
; AL: 0; CS: High between RD; Command,
; AL: 0; CS: High between WR; Command,
a)
; AL: 0; CS: High between REF; Com-
a)
; AL: 0; CS, Command, Address,
e)
16
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