H5TQ4G43AMR HYNIX [Hynix Semiconductor], H5TQ4G43AMR Datasheet - Page 22

• Manufacturer Part Number: H5TQ4G43AMR
• Description: 4Gb DDR3 SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Table 8 - IDD4W Measurement-Loop Pattern
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 9 - IDD5B Measurement-Loop Pattern
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.0 / Dec. 2009
0
1
2
3
4
5
6
7
0
1
2
0
1
2,3
4
5
6,7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
0
1.2
3,4
5...8
9...12
13...16
17...20
21...24
25...28
29...32
33...nRFC-1
repeat Sub-Loop 0, but BA[2:0] = 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 0, but BA[2:0] = 3
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 0, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 0, but BA[2:0] = 7
repeat cycles 1...4, but BA[2:0] = 1
repeat cycles 1...4, but BA[2:0] = 2
repeat cycles 1...4, but BA[2:0] = 3
repeat cycles 1...4, but BA[2:0] = 4
repeat cycles 1...4, but BA[2:0] = 5
repeat cycles 1...4, but BA[2:0] = 6
repeat cycles 1...4, but BA[2:0] = 7
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
D, D
D, D
D,D
D,D
REF
WR
WR
D
D
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
a)
a)
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
F
0
0
0
0
0
0
0
0
0
00000000
00110011
Data
Data
-
-
-
-
-
-
-
b)
b)
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