H5TQ4G43AMR HYNIX [Hynix Semiconductor], H5TQ4G43AMR Datasheet - Page 8

• Manufacturer Part Number: H5TQ4G43AMR
• Description: 4Gb DDR3 SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 1.0 / Dec. 2009
Note:
Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination.
DQSU, DQSU,
TDQS, TDQS
DQSL, DQSL
DQU, DQL,
DQS, DQS,
Symbol
V
RESET
V
V
V
REFDQ
V
REFCA
V
DQ
NC
ZQ
NF
DDQ
SSQ
DD
SS
Input /
Output
Input /
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Type
Input
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when
RESET is HIGH. RESET must be HIGH during normal operation.
RESET is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of V
1.20V for DC high and 0.30V for DC low.
Data Input/ Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. The data strobe DQS, DQSL, and DQSU are paired with differential
signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the
system during reads and writes. DDR3 SDRAM supports differential data strobe only and
does not support single-ended.
Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via
Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance
function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11
= 0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/x16
DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.
No Connect: No internal electrical connection is present.
No Function
DQ Power Supply: 1.5 V +/- 0.075 V
DQ Ground
Power Supply: 1.5 V +/- 0.075 V
Ground
Reference voltage for DQ
Reference voltage for CA
Reference Pin for ZQ calibration
Function
DD
, i.e.
8