H5TQ4G43AMR HYNIX [Hynix Semiconductor], H5TQ4G43AMR Datasheet - Page 3

• Manufacturer Part Number: H5TQ4G43AMR
• Description: 4Gb DDR3 SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Description
The H5TQ4G43AMR-xxC, H5TQ4G83AMR-xxC are a
Synchronous DRAM, ideally suited for the main memory applications which requires large memory density
and high bandwidth. Hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising
and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the
CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high
bandwidth.
Device Features and Ordering Information
FEATURES
* This product in compliance with the RoHS directive.
Rev. 1.0 / Dec. 2009
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK
• DM masks write data-in at the both rising and falling
• All addresses and control inputs except data,
• Programmable CAS latency 6, 7, 8, 9, 10 and (11)
• Programmable additive latency 0, CL-1, and CL-2
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble
• BL switch on the fly
transition
edges of the data strobe
data strobes and data masks latched on the
rising edges of the clock
supported
supported
sequential and interleave mode
4,294,967,29-bit
• 8banks
• Average Refresh Cycle (Tcase of 0
• Auto Self Refresh supported
• JEDEC standard 82ball FBGA(x4/x8)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
- 7.8 µs at 0
- 3.9 µs at 85
CMOS Double Data Rate III (DDR3)
o
C ~ 85
o
C ~ 95
o
C
o
C
o
C~ 95
o
C)
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