H5TQ4G43AMR HYNIX [Hynix Semiconductor], H5TQ4G43AMR Datasheet - Page 19

• Manufacturer Part Number: H5TQ4G43AMR
• Description: 4Gb DDR3 SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Table 4 - IDD1 Measurement-Loop Pattern
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.
Rev. 1.0 / Dec. 2009
0
1
2
3
4
5
6
7
0
1,2
3,4
...
nRCD
...
nRAS
...
1*nRC+0
1*nRC+1,2
1*nRC+3,4
...
1*nRC+nRCD
...
1*nRC+nRAS
...
2*nRC
4*nRC
6*nRC
8*nRC
10*nRC
12*nRC
14*nRC
repeat pattern 1...4 until nRCD - 1, truncate if necessary
repeat pattern 1...4 until nRAS - 1, truncate if necessary
repeat pattern 1...4 until nRC - 1, truncate if necessary
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
D, D
D, D
D, D
D, D
ACT
PRE
ACT
PRE
RD
RD
0
1
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
1
0
1
1
1
0
1
0
a)
1
0
1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
F
F
0
0
0
0
0
0
0
0
0
0
00000000
00110011
Data
-
-
-
-
-
-
-
-
b)
19