H5TQ4G43AMR HYNIX [Hynix Semiconductor], H5TQ4G43AMR Datasheet - Page 27
H5TQ4G43AMR
Manufacturer Part Number
H5TQ4G43AMR
Description
4Gb DDR3 SDRAM
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
1.H5TQ4G43AMR.pdf
(30 pages)
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DDR3-1066 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 29.
Rev. 1.0 / Dec. 2009
Internal read command to
ACT to internal read or
CL = 5
CL = 6
CL = 7
CL = 8
ACT to PRE command
PRE command period
ACT to ACT or REF
command period
write delay time
Supported CWL Settings
Parameter
Supported CL Settings
first data
CL - nRCD - nRP
period
Speed Bin
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
Symbol
t
t
t
t
t
t
t
t
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
t
t
t
t
t
RCD
RAS
AA
RP
RC
13.125
13.125
13.125
50.625
1.875
1.875
min
37.5
2.5
DDR3-1066F
Reserved
Reserved
Reserved
Reserved
Reserved
7-7-7
6, 7, 8
5, 6
9 * tREFI
< 2.5
< 2.5
max
3.3
20
—
—
—
Unit
n
n
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
1, 2, 3, 4, 5
1, 2, 3, 5
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3
Note
4
4
4
27
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