K9K1208U0A-YCB0 Samsung semiconductor, K9K1208U0A-YCB0 Datasheet

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 Document Title 64M x 8 Bit NAND Flash Memory Revision History Revision No History 0.0 1. Initial issue - Changed /SE(pin # 6, Spare Area Enable) pin to N Connection). So, /SE pin is don’ t-cared regardless of external logic input level and is fixed as low internally. 1. Changed plane address in Copy-Back Program ...

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... K9K1208U0A s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K1208U0A-YCB0/YIB0 is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requir- ing non-volatility. PIN DESCRIPTION N ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 Figure 1. FUNCTIONAL BLOCK DIAGRAM Command CE Control Logic RE & High Voltage WE CLE Figure 2. ARRAY ORGANIZATION 128K Pages 1st half Page Register (=4,096 Blocks) (=256 Bytes) 512B Byte Page Register 512 Byte I/O 0 1st Cycle A 0 2nd Cycle ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 PRODUCT INTRODUCTION The K9K1208U0A is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col- umns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 PIN DESCRIPTION Command Latch Enable(CLE) The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. Address Latch Enable(ALE) The ALE input controls the activating path for address to the internal address registers ...

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... Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, K9K1208U0A-YCB0 Parameter Supply Voltage ...

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... Invalid blocks are defined as blocks that contain one or more bad bits to access these invalid blocks for program and erase. 2. The 1st block, which is placed on 00h block address, is guaranteed valid block AC TEST CONDITION (K9K1208U0A-YCB0 :TA K9K1208U0A-YIB0:TA=- VCC=2.7V~3.6V unless otherwise) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (3 ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 AC Timing Characteristics for Command / Address / Data Input Parameter CLE setup Time CLE Hold Time CE setup Time CE Hold Time WE Pulse Width ALE setup Time ALE Hold Time Data setup Time Data Hold Time Write Cycle Time WE High Hold Time NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns. ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 NAND Flash Technical Notes (Continued) Error in write or read operation Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Erase Error I Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 Pointer Operation of K9K1208U0A Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’ 00h’ command sets the pointer to ’ A’ area(0~255byte), ’ 01h’ command sets the pointer to ’ B’ area(256~511byte), and ’ 50h’ command sets the pointer to ’ ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 System Interface Using CE don’ t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 * Command Latch Cycle CLE CE WE ALE I Address Latch Cycle t CLS CLE ALS ALE I CLH CLS ALS ALH Command ALH ALS ALH ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 * Input Data Latch Cycle CLE CE t ALS ALE Sequential Out Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load DIN 1 DIN 0 (CLE=L, WE=H, ALE=L) ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 * Status Read Cycle CLE I READ1 OPERATION (READ ONE PAGE) CLE ALE RE 00h or 01h I Column Address R/B t CLS t CLH WHR 70h AR2 ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 READ1 OPERATION (INTERCEPTED BY CE) CLE CE WE ALE 00h or 01h I Column Address R/B READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE I/O ~ 50h R/B M Address AR2 Dout ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 SEQUENTIAL ROW READ OPERATION (WITHIN A BLOCK) CLE CE WE ALE RE 00h I R/B M PAGE PROGRAM OPERATION CLE ALE RE I/O ~ 80h Sequential Data Column Input Command Address R/B Dout Ready Busy ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 BLOCK ERASE OPERATION CLE ALE RE I/O ~ 60h Page(Row) Address R/B Auto Block Erase Setup Command MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE 90h I Read ID Command (ERASE ONE BLOCK DOh Busy Erase Command ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg- ister along with four address cycles. Once the command is latched, it does not need to be written for the following page read opera- tion ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 Figure 4. Read2 Operation CLE CE WE ALE R/B RE 50h Start Add.(4Cycle) I & Don t Care) Figure 5. Sequential Row Read1 Operation R/B I 00h Start Add.(4Cycle) 01h & (00h Command) 1st half array Data Field The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read- out, the sequential read operation must be terminated by bringing CE high ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 Figure 6. Sequential Row Read2 Operation R/B I/O ~ Start Add.(4Cycle 50h & Don t Care) PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 2 for main array and 3 for spare array ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 COPY-BACK PROGRAM The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high ...

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... K9K1208U0A-YCB0, K9K1208U0A-YIB0 DATA PROTECTION The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down as shown in Figure 11. The two step command sequence for program/erase provides additional software protection ...

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Package Dimensions PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 ¡Æ 0~8 0.45~0.75 0.018~0.030 20.00 0.20 0.787 0.008 18.40 0.10 0.724 0.004 27 FLASH MEMORY Unit :mm/Inch #48 #25 1.00 0.05 ...