K9K1208U0A-YCB0 Samsung semiconductor, K9K1208U0A-YCB0 Datasheet - Page 13

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K9K1208U0A-YCB0

Manufacturer Part Number
K9K1208U0A-YCB0
Description
64M x 8 Bit NAND Flash Memory
Manufacturer
Samsung semiconductor
Datasheet
System Interface Using CE don’ t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Figure 3. Program Operation with CE don’ t-care.
I/O
K9K1208U0A-YCB0, K9K1208U0A-YIB0
CLE
Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
CE
WE
I/O
ALE
Figure 4. Read Operation with CE don’ t-care.
CE
WE
CLE
ALE
R/B
CE
WE
RE
0
0
~
~
7
7
(Min. 10ns)
t
CS
00h
80h
Start Add.(4Cycle)
Start Add.(4Cycle)
t
WP
t
CH
Must be held
low during tR.
t
R
Data Input
13
I/O
CE
RE
0
~
Timing requirements : If CE is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
7
CE don’ t-care
(Max. 45ns)
t
CE don’ t-care
Data Output(sequential)
CEA
t
REA
FLASH MEMORY
Data Input
out
10h

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