K9K1208U0A-YCB0 Samsung semiconductor, K9K1208U0A-YCB0 Datasheet - Page 25

• Manufacturer Part Number: K9K1208U0A-YCB0
• Description: 64M x 8 Bit NAND Flash Memory
• Manufacturer: Samsung semiconductor

RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 10 below.
Figure 10. RESET Operation
R/B
I/O
Table3. Device Status
K9K1208U0A-YCB0, K9K1208U0A-YIB0
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper
operation and the value may be calculated by the following equation.
0
~
7
V
Operation Mode
CC
GND
FFh
Device
R/B
open drain output
Rp
After Power-up
Read 1
t
RST
where I
R/B pin.
Rp =
25
L
V
is the sum of the input currents of all devices tied to the
CC
(Max.) - V
I
OL
+ I
OL
L
(Max.)
Waiting for next command
FLASH MEMORY
After Reset
=
8mA + I
3.2V
L