YMF754-V ETC, YMF754-V Datasheet - Page 17

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YMF754-V

Manufacturer Part Number
YMF754-V
Description
DS-1E
Manufacturer
ETC
Datasheet
YMF754
3Ch: Interrupt Line
3Dh: Interrupt Pin
3Eh: Minimum Grant
3Fh: Maximum Latency
b[7:0] ..........Interrupt Line
b[7:0] ..........Interrupt Pin
b[7:0] ..........Minimum Grant
b[7:0] ..........Maximum Latency
This register indicates the interrupt channel that INTA# is assigned to.
DS-1E supports INTA# only. This register is hardwired to 01h.
This register indicates the length of the burst period required by DS-1E.
This register is hardwired to 05h.
This register indicates how often DS-1E generates the Bus Master Request.
This register is hardwired to 19h.
b7
b7
b7
b7
Read / Write
Default: 00h
Access Bus Width: 8, 16, 32-bit
Read Only
Default: 01h
Access Bus Width: 8, 16, 32-bit
Read Only
Default: 05h
Access Bus Width: 8, 16, 32-bit
Read Only
Default: 19h
Access Bus Width: 8, 16, 32-bit
b6
b6
b6
b6
b5
b5
b5
b5
Maximum Latency
Minimum Grant
Interrupt Line
Interrupt Pin
b4
b4
b4
b4
b3
b3
b3
b3
b2
b2
b2
b2
b1
b1
b1
b1
-17-
b0
b0
b0
b0
June 28, 1999

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