YMF754-V ETC, YMF754-V Datasheet - Page 18

• Manufacturer Part Number: YMF754-V
• Description: DS-1E
• Manufacturer: ETC

YMF754
40-41h: Legacy Audio Control
b0................SBEN: Sound Blaster Enable
b1................FMEN: FM Synthesizer Enable
b2................JPEN: Joystick Port Enable
b3................MEN: MPU401 Enable
b4................MIEN: MPU401 IRQ Enable
b5................I/O: I/O Address Aliasing Control
LAD
This bit enables the mapping of the Sound Blaster Pro block in the I/O space specified by 62-63h: Sound
Blaster Base Address register, when LAD is set to “0”.
This bit enables the mapping of the FM Synthesizer block in the I/O space specified by 60-61h: FM
Synthesizer Base Address register when LAD is set to “0”. FM Synthesizer registers can be accessed via
SB I/O space, while the SB block is enabled, even if FMEN is set to “0”.
After setting FMEN to “1”, about 100 msec is necessary before accessing these I/O space.
This bit enables the mapping of the Joystick block in the I/O space specified by 66-67h: Joystick Base
Address register, when LAD is set to “0”.
This bit enables the mapping of the MPU401 block in the I/O space specified by 64-65h: MPU401 Base
Address register, when LAD is set to “0”.
This bit enables the interrupt service of MPU401, when LAD is set to “0” and MEN is set to “1”.
MPU401 generates an interrupt signal when it receives any kind of MIDI data from the RXD pin.
This bit selects the number of bits to decode for the I/O address of each block.
b15
“0”: Disable the mapping of the SB block to the I/O space
“1”: Enable the mapping of the SB block to the I/O space
“0”: Disable the mapping of the FM Synthesizer block to the FMIO space
“1”: Enable the mapping of the FM Synthesizer block to the FMIO space
“0”: Disable the mapping of the Joystick block
“1”: Enable the mapping of the Joystick block
“0”: Disable the mapping of the MPU401 block
“1”: Enable the mapping of the MPU401 block
“0”: The MPU401 block can not use the interrupt service.
“1”: The MPU401 block can use interrupt signals determined by the MPUIRQ bits.
“0”: 16-bit address decode
“1”: 10-bit address decode
Read / Write
Default: 907Fh
Access Bus Width: 8, 16, 32-bit
SIEN
b14
b13
MPUIRQ
b12
b11
(default)
b10
SBIRQ
b9
-18-
b8
(default)
(default)
b7
SDMA
b6
(default)
I/O
b5
MIEN
(default)
b4
MEN
b3
(default)
June 28, 1999
JPEN FMEN SBEN
b2
b1
b0