YMF754-V ETC, YMF754-V Datasheet - Page 53

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YMF754-V

Manufacturer Part Number
YMF754-V
Description
DS-1E
Manufacturer
ETC
Datasheet
YMF754
4. AC Characteristics
4-1. Master Clock
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=2.5±0.2 V, LVDD=2.5±0.2 V
4-2. Reset
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=2.5±0.2 V, LVDD=2.5±0.2 V, C
Reset Active Time after Power Stable
XI24 Cycle Time
XI24 High Time
XI24 Low Time
Power Stable to Reset Rising Edge
Reset Slew Rate
CVDD, LVDD
PVDD, VDD
Item
(Fig.2)
Item
RST#
XI24
(Fig.1)
Fig.1: XI24 Master Clock timing
Symbol
t
t
t
XIHIGH
XILOW
XICYC
Fig.2: PCI Reset timing
Symbol
t
t
RSTOFF
XIHIGH
t
RST
-
Min.
3.0 V
-53-
13
13
2.3 V
-
t
XICYC
Min.
10
50
2.3 V
1
40.69
Typ.
t
-
-
XILOW
t
RSTOFF
Typ.
-
-
-
Max.
24
24
-
t
RST
1.0 V
1.65 V
Max.
-
-
-
Unit
ns
ns
ns
mV/ns
Unit
0.8 V
ms
ms
L
=50 pF
June 28, 1999

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