CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 75

• Manufacturer Part Number: CN8330EPD
• Description: DS3/E3 Framer with 52 Mbps HDLC Controller
• Manufacturer: CONEXANT [Conexant Systems, Inc]

Table 4-1. Microprocessor Interface Timing (1 of 2)
100441E
t
t
t
t
t
t
t
t
t
t
as
cale
ah
rwa
adwrh
adrdl
wrw
wrw
rdd
rdh
(Read Operation)
(Write Operation)
Symbol
Address Setup before ALE Low
Controller ALE Pulse Width
Address Hold after ALE Low
RD*/WR* High to ALE High
Address/Select to WR* High
Address/Select to RD* Low
RD* Pulse Width
WR* Pulse Width
RD* Low to Data Available
Read Data Hold Time
4.0 Mechanical/Electrical Specifications
4.1 Timing Requirements
Table 4-1
interface. The parameter t
This clock signal is used in the read circuit of the microprocessor to ensuring no
status events are missed and that counter values are accurately read.
ensuring that changing status and error counts are properly processed. If a gapped
clock is applied to the circuit, it is sufficient to allow three receive clock cycles
between read strobes to allow a latching circuit to clear in the microprocessor
interface.
Read operation requires the read strobe to be low for three t
(1)
and
Parameter
(2)
Figure 4-1
Conexant
illustrate the timing requirements for the microprocessor
cyc
is the period of the receive DS3/E3 clock (DS3CKI).
4
3 × t cyc
Min.
117
100
34
10
10
17
—
7
3
Typical
—
—
—
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
—
30
—
cyc
clock cycles
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4-1