CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 21

• Manufacturer Part Number: CN8330EPD
• Description: DS3/E3 Framer with 52 Mbps HDLC Controller
• Manufacturer: CONEXANT [Conexant Systems, Inc]

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Table 1-2. Hardware Signal Definitions (4 of 5)
100441E
RXBCK/RXGAPCK
RXPOS, RXNEG
RXCCK/TXNRZ
RDAT[0]/LOS
RDAT[1]/OOF
RDAT[2]/AIS
Pin Label
DS3CKI
RXMSY
RXDAT
RXCLK
RXCKI
CBITO
FIFEN
DS3 Receive Line Clock In
Receive Bipolar
Positive/Negative
Receive Dejittered
Clock In
FIFO Enable
Receive Serial Data
Receive M-Sync
Receive Clock
Receive Byte/Gapped Clock
Receive C/N-Bit Serial Out
Receive C/N-Bit Clock
Out/Transmit NRZ
Receive Data Byte 0/Loss of
Signal
Receive Data Byte 1/
Out of Frame
Receive Data Byte 2/Alarm
Indication Signal
Signal Name
Conexant
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
Clock input DS3CKI should be connected to a 44.736
MHz source (34.368 MHz for the E3) derived from
incoming receive data.
The input positive and negative pulses are sampled
on the rising edge of the receiver input clock
(DS3CKI) and should be a full clock period wide.
Used to read the received data out of the internal
FIFO (required only if FIFO is enabled). If unused, tie
to ground.
FIFO, used to dejitter the received data by using the
dejittered clock input, RXCKI. When FIFEN is low, the
FIFO is bypassed and the serial data is output with
respect to the incoming clock, DS3CKI.
RXDAT is the serial data bit stream clocked out on
the rising edge of RXCLK.
The M-frame synchronization output recovered from
the incoming serial data stream.
The receive clock used internally to clock out the
serial data stream onto RXDAT.
When in serial mode, RXGAPCK provides a gapped
clock signal during every overhead bit (in both DS3
and E3 modes). In parallel mode, RXBCK is used to
internally clock out the receive byte-oriented data on
RDAT[7:0].
A clock that indicates transitions in the CBIT0 signal.
In PPDL-only mode, transmit NRZ data is available
on this pin.
Part of the 8-bit data bus output from the PPDL
receiver when parallel mode is enabled. When
parallel mode is disabled, this pin is an active-high
monitor output indicating loss of signal.
Part of the 8-bit data bus output from the PPDL
receiver when parallel mode is enabled. When
parallel mode is disabled, this pin is an active-high
monitor output indicating out-of-frame.
Part of the 8-bit data bus output from the PPDL
receiver when parallel mode is enabled. When
parallel mode is disabled, this pin is an active-high
monitor output indicating alarm indication signal.
The receive serial C-bit (DS3 mode) or N-bit (E3
mode) data. CBITO changes on the rising edge of
RXCCK.
An active-high input which enables the internal
Definition
1.0 Product Description
1.1 Pin Descriptions
1-11