CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 70

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CN8330EPD

Manufacturer Part Number
CN8330EPD
Description
DS3/E3 Framer with 52 Mbps HDLC Controller
Manufacturer
CONEXANT [Conexant Systems, Inc]
Datasheet
3.0 Registers
3.2 Status Registers
The DS3 Disagreement Counter consists of two 4-bit counters. Both counters indicate 0 through 15 counts of
disagreements in either the two X (yellow alarm) bits or the two P (parity) bits. If the interrupt is not enabled,
the counters saturate at 15 when more than 15 counts are received. Saturation of either 4-bit counter will
generate a disagreement counter interrupt indication in Counter Interrupt Status Register [SR01;0x11]. If the
disagreement interrupt is enabled, the counters will roll over and continue counting after 15 error counts and
generate an interrupt in Counter Interrupt Status Register and on the CNTINT/LINELB pin.
ParDgrCtr[3:0]
XDgrCtr[3:0]
FerrCtr[7:0]
DS3PthCtr[7:0]
3-12
0x21—DS3 Disagreement Counter (SR08)
0x22—DS3/E3 Frame Error Counter (SR09)
0x23—DS3 Path Parity Error Counter (SR10)
DS3PthCtr[7]
ParDgrCtr[3]
FerrCtr[7]
7
7
7
DS3PthCtr[6]
ParDgrCtr[2]
Parity-Bit Disagreement Counter—If the two P-bits in an M-frame are in disagreement, the
P-bit disagreement counter nibble will be incremented.
X-Bit Disagreement Counter—If the two X-bits in an M-frame are in disagreement (due to
line errors), the X-bit disagreement counter nibble will be incremented.
FerrCtr[6]
Frame Error Counter—Increments with each error in the M- or F-bit framing pattern in DS3
mode and with each error in the FAS pattern in E3 mode. Errors are still counted during an
OOF condition (OOFAlm = 1).
DS3 Path Parity Error Counter—Increments for each M-frame in which the calculated parity
of the received data bits of the previous M-frame do not match a majority vote of the three
received CP bits (C-bits in subframe 30).
6
6
6
DS3PthCtr[5]
ParDgrCtr[1]
FerrCtr[5]
5
5
5
DS3PthCtr[4]
ParDgrCtr[0]
FerrCtr[4]
4
4
4
Conexant
DS3PthCtr[3]
XDgrCtr[3]
FerrCtr[3]
3
3
3
DS3/E3 Framer with 52 Mbps HDLC Controller
DS3PthCtr[2]
XDgrCtr[2]
FerrCtr[2]
2
2
2
DS3PthCtr[1]
XDgrCtr[1]
FerrCtr[1]
1
1
1
DS3PthCtr[0]
XDgrCtr[0]
FerrCtr[0]
CN8330
100441E
0
0
0

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