K9K1G08R0B SAMSUNG [Samsung semiconductor], K9K1G08R0B Datasheet - Page 27

• Manufacturer Part Number: K9K1G08R0B
• Description: 128M x 8 Bit NAND Flash Memory
• Manufacturer: SAMSUNG [Samsung semiconductor]

Device Operation
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg-
ister along with four address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are trans-
ferred to the data registers in less than 15µs(t
ing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns(1.8V device : 60ns) cycle
time by sequentially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up
to the last column address.
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of
bytes 512 to 527 may be selectively accessed by writing the Read2 command. Addresses A
spare area while addresses A
sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 com-
mand(00h/01h) is needed to move the pointer back to the main area. Figures 9 to 12 show typical sequence and timings for each
read operation.
K9K1G08R0B
K9K1G08B0B
K9K1G08U0B
4
to A
7
are ignored. Unless the operation is aborted, the page address is automatically incremented for
R
). The system controller can detect the completion of this data transfer(tR) by analyz-
27
0
to A
FLASH MEMORY
3
set the starting address of the
Advance