PIC18F2420-I/SOC01 Microchip, PIC18F2420-I/SOC01 Datasheet - Page 104
![no-image](/images/no-image-200.jpg)
PIC18F2420-I/SOC01
Manufacturer Part Number
PIC18F2420-I/SOC01
Description
28 pin, 16 kb flash, 3804 ram, 25 i/o...
Manufacturer
Microchip
Datasheet
1.PIC18F2420-ISOC01.pdf
(412 pages)
- Current page: 104 of 412
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PIC18F2420/2520/4420/4520
9.5
The RCON register contains flag bits which are used to
determine the cause of the last Reset or wake-up from
Idle or Sleep modes. RCON also contains the IPEN bit
which enables interrupt priorities.
REGISTER 9-10:
DS39631E-page 102
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
IPEN
RCON Register
Actual Reset values are determined by device configuration and the nature of the device Reset. See
Register 4-1 for additional information.
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
SBOREN: Software BOR Enable bit
For details of bit operation, see Register 4-1.
Unimplemented: Read as ‘0’
RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-1.
TO: Watchdog Timer Time-out Flag bit
For details of bit operation, see Register 4-1.
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 4-1.
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-1.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
SBOREN
R/W-1
RCON: RESET CONTROL REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
U-0
—
(1)
R/W-1
RI
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
The operation of the SBOREN bit and the Reset flag
bits is discussed in more detail in Section 4.1 “RCON
Register”.
R-1
TO
R-1
PD
© 2008 Microchip Technology Inc.
x = Bit is unknown
R/W-0
POR
(1)
R/W-0
BOR
bit 0
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