PIC18F2420-I/SOC01 Microchip, PIC18F2420-I/SOC01 Datasheet - Page 300

• Manufacturer Part Number: PIC18F2420-I/SOC01
• Description: 28 pin, 16 kb flash, 3804 ram, 25 i/o...
• Manufacturer: Microchip

PIC18F2420/2520/4420/4520
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39631E-page 298
Q Cycle Activity:
After Interrupt
operation
Decode
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL
Q1
No
operation
operation
Return from Interrupt
RETFIE {s}
s ∈ [0,1]
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL;
if s = 1,
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
GIE/GIEH, PEIE/GIEL.
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low-priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers, WS,
STATUSS and BSRS, are loaded into
their corresponding registers, W,
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs (default).
1
2
RETFIE
0000
Q2
No
No
1
0000
operation
operation
=
=
=
=
=
Q3
No
No
TOS
WS
BSRS
STATUSS
1
0001
Set GIEH or
from stack
operation
POP PC
GIEL
Q4
No
000s
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
TABLE
Q Cycle Activity:
:
:
:
CALL TABLE ; W contains table
ADDWF PCL
RETLW k0
RETLW k1
RETLW kn
Before Instruction
After Instruction
operation
Decode
W
W
Q1
No
; offset value
; W now has
; table value
; W = offset
; Begin table
;
; End of table
=
=
operation
Return Literal to W
RETLW k
0 ≤ k ≤ 255
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
None
W is loaded with the 8-bit literal ‘k’. The
program counter is loaded from the top
of the stack (the return address). The
high address latch (PCLATH) remains
unchanged.
1
2
literal ‘k’
Read
0000
Q2
No
07h
value of kn
© 2008 Microchip Technology Inc.
1100
operation
Process
Data
Q3
No
kkkk
from stack,
Write to W
operation
POP PC
Q4
No
kkkk