PIC18F2420-I/SOC01 Microchip, PIC18F2420-I/SOC01 Datasheet - Page 189

• Manufacturer Part Number: PIC18F2420-I/SOC01
• Description: 28 pin, 16 kb flash, 3804 ram, 25 i/o...
• Manufacturer: Microchip

17.4.7
In I
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
Q2 and Q4 clocks. In I
reloaded automatically.
FIGURE 17-17:
TABLE 17-3:
© 2008 Microchip Technology Inc.
Note 1:
2
C Master mode, the Baud Rate Generator (BRG)
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
BAUD RATE
F
CY
2
C interface does not conform to the 400 kHz I
I
2
C™ CLOCK RATE W/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C Master mode, the BRG is
SSPM<3:0>
SCL
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
CY
SSPM<3:0>
CY
* 2
PIC18F2420/2520/4420/4520
) on the
Reload
Control
CLKO
Reload
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
2
BRG Down Counter
C specification (which applies to rates greater than
SSPADD<6:0>
BRG Value
0Ch
1Fh
18h
63h
09h
27h
02h
09h
00h
F
OSC
(2 Rollovers of BRG)
/4
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
DS39631E-page 187
100 kHz
308 kHz
100 kHz
100 kHz
F
SCL
(1)
(1)
(1)
(1)