PIC18F2420-I/SOC01 Microchip, PIC18F2420-I/SOC01 Datasheet - Page 163

• Manufacturer Part Number: PIC18F2420-I/SOC01
• Description: 28 pin, 16 kb flash, 3804 ram, 25 i/o...
• Manufacturer: Microchip

17.0
17.1
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D Converters, etc. The MSSP
module can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
The I
hardware:
• Master mode
• Multi-Master mode
• Slave mode
17.2
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual configuration bits
differ significantly depending on whether the MSSP
module is operated in SPI or I
Additional details are provided under the individual
sections.
© 2008 Microchip Technology Inc.
- Full Master mode
- Slave mode (with general address call)
2
C interface supports the following modes in
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
Control Registers
2
C)
2
C mode.
PIC18F2420/2520/4420/4520
17.3
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes
communication, typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1:
HLVDIN/C2OUT
RC4/SDI/SDA
RC3/SCK/
RA5/AN4/SS/
RC5/SDO
SCL
SPI Mode
of
SPI
Read
are
SS Control
Select
SMP:CKE
Edge
MSSP BLOCK DIAGRAM
(SPI MODE)
Select
bit 0
Edge
Enable
supported.
TRIS bit
Data to TX/RX in SSPSR
SSPBUF reg
2
SSPSR reg
SSPM<3:0>
Clock Select
4
DS39631E-page 161
2
To
(
Prescaler
4, 16, 64
TMR2 Output
Write
Clock
Shift
accomplish
Data Bus
Internal
2
T
OSC
)