PIC18F2420-I/SOC01 Microchip, PIC18F2420-I/SOC01 Datasheet - Page 45
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PIC18F2420-I/SOC01
Manufacturer Part Number
PIC18F2420-I/SOC01
Description
28 pin, 16 kb flash, 3804 ram, 25 i/o...
Manufacturer
Microchip
Datasheet
1.PIC18F2420-ISOC01.pdf
(412 pages)
- Current page: 45 of 412
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4.2
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR Reset path which detects and ignores small
pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
In PIC18F2420/2520/4420/4520 devices, the MCLR
input can be disabled with the MCLRE Configuration
bit. When MCLR is disabled, the pin becomes a digital
input. See Section 10.5 “PORTE, TRISE and LATE
Registers” for more information.
4.3
A Power-on Reset pulse is generated on-chip
whenever V
allows the device to start in the initialized state when
V
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 kΩ to 10 kΩ) to V
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
V
time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a POR occurs;
it does not change for any other Reset event. POR is
not reset to ‘1’ by any hardware event. To capture
multiple events, the user manually resets the bit to ‘1’
in software following any POR.
© 2008 Microchip Technology Inc.
DD
DD
is adequate for operation.
is specified (parameter D004). For a slow rise
Master Clear (MCLR)
Power-on Reset (POR)
DD
rises above a certain threshold. This
DD
. This will
PIC18F2420/2520/4420/4520
FIGURE 4-2:
Note 1: External Power-on Reset circuit is required
V
2: R < 40 kΩ is recommended to make sure that
3: R1 ≥ 1 kΩ will limit any current flowing into
DD
D
only if the V
The diode D helps discharge the capacitor
quickly when V
the voltage drop across R does not violate
the device’s electrical specification.
MCLR from external capacitor C, in the event
of MCLR/V
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
V
DD
R
C
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD
PP
R1
DD
power-up slope is too slow.
pin breakdown, due to
powers down.
DD
PIC18FXXXX
MCLR
POWER-UP)
DS39631E-page 43
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