MT48LC2M32B2TG-6 :G Micron, MT48LC2M32B2TG-6 :G Datasheet

no-image

MT48LC2M32B2TG-6 :G

Manufacturer Part Number
MT48LC2M32B2TG-6 :G
Description
DRAM Chip SDRAM 64M-Bit 3.3V 86-Pin TSOP-II
Manufacturer
Micron
Datasheet
Synchronous DRAM
MT48LC2M32B2 – 512K x 32 x 4 banks
For the latest data sheet, refer to Micron’s Web site
Features
• PC100 functionality
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can be
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
• Self refresh mode (not available on AT devices)
• Refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency (CL) of 1, 2, and 3
Notes: 1. Off-center parting line.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_1.fm - Rev. J 12/08 EN
Options
• Configuration
• Plastic package – OCPL
• Timing (cycle time)
• Die revision
• Operating temperature range
edge of system clock
changed every clock cycle
and auto refresh modes
– 64ms, 4,096-cycle refresh (15.6µs/row)
– 16ms, 4,096-cycle refresh (3.9µs/row)
– 2 Meg x 32 (512K x 32 x 4 banks)
– 86-pin TSOP II (400 mil)
– 86-pin TSOP II (400 mil) Pb-free
– 90-ball VFBGA (8mm x 13mm) Pb-free
– 5ns (200 MHz)
– 5.5ns (183 MHz)
– 6ns (166 MHz)
– 7ns (143 MHz)
– Commercial (0° to +70°C)
– Industrial (–40°C to +85°C)
– Automotive (–40°C to +105°C)
(commercial, industrial)
(automotive)
2. Available on -6 and -7.
3. Contact Micron for product availability.
Products and specifications discussed herein are subject to change by Micron without notice.
1
Marking
2M32B2
None
AT
-55
IT
TG
B5
:G
-5
-6
-7
P
2
3
1
Table 1:
Table 2:
Table 3:
Notes: 1. FBGA Device Decode: http://
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
MT48LC2M32B2TG
MT48LC2M32B2P
MT48LC2M32B2B5
Speed
Grade
-55
-5
-6
-7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Part Number
www.micron.com/support/FBGA/FBGA.asp
Frequency
200 MHz
183 MHz
166 MHz
143 MHz
Address Table
Key Timing Parameters
CL = CAS (READ) latency
64Mb (x32) SDRAM Part Number
Clock
MT48LC2M32B2P-7:G
Part Number Example:
1
Access
CL = 3
Time
4.5ns
5.5ns
5.5ns
5ns
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
512K x 32 x 4 banks
Architecture
4 (BA0, BA1)
2K (A0–A10)
2 Meg x 32
256 (A0–A7)
Setup
2 Meg x 32
2 Meg x 32
2 Meg x 32
Time
1.5ns
1.5ns
1.5ns
2ns
4K
Features
Hold
Time
1ns
1ns
1ns
1ns

Related parts for MT48LC2M32B2TG-6 :G

MT48LC2M32B2TG-6 :G Summary of contents

Page 1

... Speed Clock Grade Frequency -5 200 MHz -55 183 MHz -6 166 MHz -7 143 MHz Marking Table 3: 64Mb (x32) SDRAM Part Number 2M32B2 Part Number TG MT48LC2M32B2TG P MT48LC2M32B2P B5 MT48LC2M32B2B5 -5 Notes: 1. FBGA Device Decode: http:// -55 www.micron.com/support/FBGA/FBGA.asp - MT48LC2M32B2P-7:G None Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 2

... Ambient and case temperatures cannot be less than –40°C or greater than 105°C PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_1.fm - Rev. J 12/08 EN ® 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 64Mb: x32 SDRAM General Description ©2001 Micron Technology, Inc. All rights reserved. ...

Page 3

... Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Electrical Specifications .43 Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Timing Diagrams .51 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32TOC.fm - Rev. J 12/08 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 ©2001 Micron Technology, Inc. All rights reserved. 64Mb: x32 SDRAM Table of Contents ...

Page 4

... VFBGA (8mm x 13mm .69 PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32LOF.fm - Rev. J 12/ RCD (MIN) when 2 < RCD (MIN)/ 4 64Mb: x32 SDRAM List of Figures .20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. ...

Page 5

... VFBGA Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Table 18: Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .47 Table 19: AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32LOT.fm - Rev. J 12/08 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. 5 ©2001 Micron Technology, Inc. All rights reserved. 64Mb: x32 SDRAM List of Tables ...

Page 6

... Functional Block Diagram BANK 3 BANK 2 BANK 1 BANK0 4 ARRAY DATA OUTPUT 32 REGISTER 8192 DATA INPUT 32 256 REGISTER (x32) Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. 4 DQM0– DQM3 DQ0– 32 DQ31 ...

Page 7

... DQ29 DQ28 37 50 DQ27 DQ26 40 47 DQ25 DQ24 Micron Technology, Inc., reserves the right to change products or specifications without notice. 7 64Mb: x32 SDRAM ©2001 Micron Technology, Inc. All rights reserved. ...

Page 8

... V DD A10 BA1 NC BA0 CS# RAS# CAS# WE# DQM0 V DQ7 DQ6 DQ5 DQ1 DQ3 DQ4 DQ0 DQ2 DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. ...

Page 9

... BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. DQ0– Input/ Data I/Os: Data bus. DQ31 Output 9 64Mb: x32 SDRAM Description Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. ...

Page 10

... A11 with stuffing options. and V Q (simultaneously) and the clock is stable (stable clock Micron Technology, Inc., reserves the right to change products or specifications without notice. 10 64Mb: x32 SDRAM Functional Description Description ©2001 Micron Technology, Inc. All rights reserved. ...

Page 11

... RFC time, during which only NOPs or COMMAND INHIBIT commands t MRD time, during which only NOP or DESELECT commands are t RFC loops is achieved. Micron Technology, Inc., reserves the right to change products or specifications without notice. 11 64Mb: x32 SDRAM Functional Description Q. ©2001 Micron Technology, Inc. All rights reserved. ...

Page 12

... Full-page bursts wrap within the page if the boundary is reached. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN Functional Description Micron Technology, Inc., reserves the right to change products or specifications without notice. 12 64Mb: x32 SDRAM ©2001 Micron Technology, Inc. All rights reserved. ...

Page 13

... Reserved Reserved Reserved Reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 13 64Mb: x32 SDRAM Functional Description A1 Address Bus Mode Register (Mx) BT Burst Length Burst Length ...

Page 14

... SDRAM Functional Description Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Cn Not supported 4... … Cn… Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 ...

Page 15

... OUT NOP NOP OUT t AC DON’T CARE UNDEFINED ≤ 200 – ≤ 183 – ≤ 166 ≤ 143 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. ...

Page 16

... – – – – L – – – – H Micron Technology, Inc., reserves the right to change products or specifications without notice. 16 64Mb: x32 SDRAM Commands ADDR DQs Notes Bank/row Bank/col Bank/col Valid 2 X Active ...

Page 17

... DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ MRD is met. Micron Technology, Inc., reserves the right to change products or specifications without notice. 17 64Mb: x32 SDRAM Commands ©2001 Micron Technology, Inc. All rights reserved. ...

Page 18

... RP) is completed. This is determined explicit PRECHARGE command was s (commercial and industrial) or 3.906 µ 18 64Mb: x32 SDRAM s (automotive) will meet the refresh µ t RFC), once every 64ms Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands ...

Page 19

... RCD specification. t RCD specification of 20ns with a 125 MHz clock (8ns period RCD (MIN (the same procedure is used to convert other Micron Technology, Inc., reserves the right to change products or specifications without notice. 19 64Mb: x32 SDRAM Commands t XSR because time is t RCD (MIN) should be divided ...

Page 20

... ACTIVE NOP NOP t RCD (MIN) t RCD (MIN) +0 8ns where x = number of clocks for equation to be true. Micron Technology, Inc., reserves the right to change products or specifications without notice. 20 64Mb: x32 SDRAM Commands READ or WRITE DON’T CARE ...

Page 21

... PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN HIGH COLUMN ADDRESS ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK ADDRESS DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. 21 64Mb: x32 SDRAM Commands ©2001 Micron Technology, Inc. All rights reserved. ...

Page 22

... READ NOP 64Mb: x32 SDRAM NOP OUT NOP NOP OUT t AC DON’T CARE UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands ...

Page 23

... NOP READ NOP NOP cycles BANK, COL OUT OUT OUT OUT Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands T7 NOP D OUT b DON’T CARE ...

Page 24

... OUT OUT READ NOP NOP NOP BANK, COL OUT OUT OUT OUT DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands ...

Page 25

... NOP NOP BANK, COL 64Mb: x32 SDRAM T3 T4 NOP WRITE BANK, COL OUT DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands ...

Page 26

... SDRAM NOP NOP WRITE BANK, COL OUT DON’T CARE met. Note that part of Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands ...

Page 27

... cycles BANK (a or all OUT OUT OUT OUT Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands T7 ACTIVE BANK a, ROW T7 ACTIVE BANK a, ROW T7 ACTIVE BANK a, ROW ...

Page 28

... BURST NOP NOP NOP TERMINATE cycles OUT OUT OUT OUT Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands T7 NOP DON’T CARE ...

Page 29

... Rev. J 12/08 EN HIGH COLUMN ADDRESS ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK ADDRESS VALID ADDRESS DON’T CARE 29 64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands ...

Page 30

... WR and sometime between the first and second clock on a “two-clock” 30 64Mb: x32 SDRAM T3 NOP t WR after the clock edge met. The Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands t WR ...

Page 31

... SDRAM T3 WRITE BANK, COL DON’T CARE NOP NOP NOP D D OUT OUT DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands ...

Page 32

... NOP ACTIVE BANK a, ROW t RP NOP NOP ACTIVE BANK BANK all) ROW DON’T CARE t RP) after the PRECHARGE command is issued. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands ...

Page 33

... NEXT WRITE TERMINATE COMMAND BANK, (ADDRESS) COL (DATA) n DON’T CARE 33 64Mb: x32 SDRAM t REF or t CKS). Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands t REF ) since no AT ...

Page 34

... NOP ( ( ) ) Input buffers gated off Exit power-down mode. Micron Technology, Inc., reserves the right to change products or specifications without notice. 34 64Mb: x32 SDRAM Commands > t CKS NOP ACTIVE t RCD t RAS t RC DON’T CARE ©2001 Micron Technology, Inc. All rights reserved. ...

Page 35

... NOP DON’T CARE NOP NOP NOP OUT OUT OUT DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands ...

Page 36

... NOP NOP Idle BANK BANK n Precharge OUT OUT OUT (BANK m) DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands OUT ...

Page 37

... T4 NOP NOP NOP NOP Precharge BANK BANK OUT OUT (BANK m) DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands Idle ...

Page 38

... Exit clock suspend Power-down entry Self refresh entry Clock suspend entry was the state of CKE at the previous result of n Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Commands Notes ...

Page 39

... Starts with registration of a WRITE command with auto precharge enabled and ends when will be in the idle state. Micron Technology, Inc., reserves the right to change products or specifications without notice. 39 64Mb: x32 SDRAM Command (Action) is HIGH (see Table 8 on page 38) and ...

Page 40

... Starts with registration of a PRECHARGE ALL command and ends t t when RP is met. After RP is met, all banks will be in the idle state. Micron Technology, Inc., reserves the right to change products or specifications without notice. 40 64Mb: x32 SDRAM Commands t MRD is met, the SDRAM will ...

Page 41

... Starts with registration of a WRITE command with auto precharge enabled and ends when will be in the idle state. Micron Technology, Inc., reserves the right to change products or specifications without notice. 41 64Mb: x32 SDRAM Commands Command (Action) ...

Page 42

... PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ met, where WR begins when the WRITE to bank m is regis- Micron Technology, Inc., reserves the right to change products or specifications without notice. 42 64Mb: x32 SDRAM Commands met, where WR begins ...

Page 43

... PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ supply relative Micron Technology, Inc., reserves the right to change products or specifications without notice. 43 64Mb: x32 SDRAM Electrical Specifications Min Max Units –1V +4.6 V – ...

Page 44

... FBGA 4-layer Notes: 1. For designs expected to last beyond the die revision listed, contact Micron Applications Engineering to confirm thermal impedance values. 2. Thermal resistance data is sampled from multiple lots and the values should be viewed as typical. 3. These are estimates; actual results may vary. ...

Page 45

... Example Temperature Test Point Location, 90-Ball FBGA (Top View) Test point PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN 22.22mm 11.11mm 8.00mm 4.00mm 13.00mm 6.50mm Micron Technology, Inc., reserves the right to change products or specifications without notice. 45 64Mb: x32 SDRAM Electrical Specifications 10.16mm 5.08mm ©2001 Micron Technology, Inc. All rights reserved. ...

Page 46

... 280 RFC = RFC (MIN 225 Symbol Symbol Micron Technology, Inc., reserves the right to change products or specifications without notice. 46 64Mb: x32 SDRAM Electrical Specifications , +3.3V ±0. Min Max Units Notes –0.3 0.8 V – ...

Page 47

... Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Units Notes ...

Page 48

... MRD ROH ( ROH (2) – – ROH (1) – – Micron Technology, Inc., reserves the right to change products or specifications without notice. 48 64Mb: x32 SDRAM Electrical Specifications -6 -7 Units Notes ...

Page 49

... levels RP; clock(s) is (are) specified as a reference undershoot: V (MIN) = -1.2V for Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. Notes 40°C ≤ T ≤ – must be pow- ...

Page 50

... Rev. J 12/ WR, and PRECHARGE commands). CKE may be used to reduce the (MIN) = 3.135V for -6, -55, and -5 speed grades 10ns and higher) in manual precharge. Micron Technology, Inc., reserves the right to change products or specifications without notice. 50 64Mb: x32 SDRAM Notes 10ns. ...

Page 51

... RFC AUTO REFRESH AUTO REFRESH Micron Technology, Inc., reserves the right to change products or specifications without notice. 51 64Mb: x32 SDRAM Timing Diagrams LOAD MODE NOP NOP NOP ( ( ...

Page 52

... Exit power-down mode 52 64Mb: x32 SDRAM Timing Diagrams CKS NOP ACTIVE ROW ROW BANK All banks idle DON’T CARE UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. ...

Page 53

... SDRAM Timing Diagrams NOP WRITE 2 COLUMN e BANK OUT Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. T9 NOP OUT DON’T CARE UNDEFINED ...

Page 54

... RP t RFC Micron Technology, Inc., reserves the right to change products or specifications without notice. 54 64Mb: x32 SDRAM Timing Diagrams AUTO NOP NOP ACTIVE ( ( REFRESH ) ) ( ( ) ...

Page 55

... RP Enter self refresh mode Exit self refresh mode (Restart refresh time base) CLK stable prior to exiting self refresh mode Micron Technology, Inc., reserves the right to change products or specifications without notice. 55 64Mb: x32 SDRAM Timing Diagrams ...

Page 56

... CMH COLUMN m 2 ALL BANKS SINGLE BANK DISABLE AUTO PRECHARGE BANK BANK RCD CAS Latency t RAS t RC Micron Technology, Inc., reserves the right to change products or specifications without notice. 56 64Mb: x32 SDRAM Timing Diagrams T4 T5 NOP ACTIVE ROW ROW BANK t AC ...

Page 57

... BANK OUT OUT OUT Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. T8 ACTIVE ROW ROW BANK DON’T CARE UNDEFINED ...

Page 58

... NOP OUT OUT OUT Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. T8 ACTIVE ROW ROW BANK DON’T CARE UNDEFINED ...

Page 59

... OUT OUT OUT BANK 0 CAS Latency - BANK 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. T8 ACTIVE ROW ROW BANK OUT t RCD - BANK 0 DON’ ...

Page 60

... m OUT OUT OUT ( ( ) ) 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved NOP NOP m+1 OUT t HZ DON’T CARE UNDEFINED ...

Page 61

... NOP NOP t CMS t CMH COLUMN m 2 BANK OUT CAS Latency Micron Technology, Inc., reserves the right to change products or specifications without notice. 61 64Mb: x32 SDRAM Timing Diagrams NOP NOP NOP NOP ...

Page 62

... IN t WR. 62 64Mb: x32 SDRAM Timing Diagrams T4 T5 PRECHARGE NOP ALL BANKS SINGLE BANK BANK t RP Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. T6 ACTIVE ROW ROW BANK DON’T CARE ...

Page 63

... NOP ALL BANKs SINGLE BANK BANK > CK). Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. T8 ACTIVE ROW ROW BANK DON’T CARE UNDEFINED ...

Page 64

... SDRAM Timing Diagrams NOP NOP NOP > CK). Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. T9 ACTIVE ROW ROW BANK DON’T CARE UNDEFINED ...

Page 65

... BANK BANK > CK). Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. T9 ACTIVE ROW ROW BANK RCD - BANK 0 ...

Page 66

... 256 locations within same row Full page completed t RP. Micron Technology, Inc., reserves the right to change products or specifications without notice. 66 64Mb: x32 SDRAM Timing Diagrams ...

Page 67

... 64Mb: x32 SDRAM Timing Diagrams NOP NOP NOP NOP DON’T CARE UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. ...

Page 68

... PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN 0.61 2X 0.10 +0.07 -0.03 2X 2.80 11.76 ±0.20 10.16 ±0.08 0.15 0.10 1.20 MAX Micron Technology, Inc., reserves the right to change products or specifications without notice. 68 64Mb: x32 SDRAM Package Dimensions SEE DETAIL A +0.03 -0.02 +0.10 0.10 -0.05 0.50 ±0.10 DETAIL A ©2001 Micron Technology, Inc. All rights reserved. ...

Page 69

... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur ...

Related keywords