MT48LC2M32B2TG-6 :G Micron, MT48LC2M32B2TG-6 :G Datasheet - Page 65
![no-image](/images/no-image-200.jpg)
MT48LC2M32B2TG-6 :G
Manufacturer Part Number
MT48LC2M32B2TG-6 :G
Description
DRAM Chip SDRAM 64M-Bit 3.3V 86-Pin TSOP-II
Manufacturer
Micron
Datasheet
1.MT48LC2M32B2B5-7G.pdf
(69 pages)
- Current page: 65 of 69
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Figure 47:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
DQML, DQMH
COMMAND
BA0, BA1
DQM /
A0-A9
CLK
CKE
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
BANK 0
T0
ROW
ROW
Alternating Write Accesses
t CKH
t CMH
t AH
t AH
t AH
t RCD - BANK 0
t RAS - BANK 0
t
t
Notes:
RC - BANK 0
RRD
t CK
T1
NOP
1. For this example, BL = 4.
2. Faster frequencies require two clocks (when
3. A8 and A9 = “Don’t Care.”
ENABLE AUTO PRECHARGE
t CMS
t CL
t DS
COLUMN m 3
BANK 0
WRITE
T2
D
IN
t CMH
t CH
t DH
m
t DS
D
IN
T3
NOP
m + 1
t DH
t DS
D
ACTIVE
BANK 1
IN
T4
ROW
ROW
m + 2
t DH
65
t RCD - BANK 1
t DS
D
IN
T5
NOP
m + 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DH
t WR - BANK 0
ENABLE AUTO PRECHARGE
t
WR >
t DS
COLUMN b 2
BANK 1
WRITE
T6
D
IN
t DH
b
t
CK).
t DS
D
NOP
IN
T7
b + 1
t RP - BANK 0
t DH
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
t DS
Timing Diagrams
D
IN
NOP
T8
b + 2
t DH
t DS
D
BANK 0
ACTIVE
T9
IN
ROW
ROW
b + 3
t
t
RCD - BANK 0
WR - BANK 1
DON’T CARE
t DH
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