MT48LC2M32B2TG-6 :G Micron, MT48LC2M32B2TG-6 :G Datasheet - Page 50
![no-image](/images/no-image-200.jpg)
MT48LC2M32B2TG-6 :G
Manufacturer Part Number
MT48LC2M32B2TG-6 :G
Description
DRAM Chip SDRAM 64M-Bit 3.3V 86-Pin TSOP-II
Manufacturer
Micron
Datasheet
1.MT48LC2M32B2B5-7G.pdf
(69 pages)
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PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
23. The clock frequency must remain constant during access or precharge states (READ,
24. Auto precharge mode only.
25. JEDEC and PC100 specify three clocks.
26.
27. V
28. Check factory for availability of specially screened devices having
WRITE, including
data rate.
t
t
CK = 7ns for -7, 6ns for -6, 5.5ns for -55, and 5ns for -5.
CK for 100 MHz and slower (
DD
(MIN) = 3.135V for -6, -55, and -5 speed grades.
t
WR, and PRECHARGE commands). CKE may be used to reduce the
50
t
CK = 10ns and higher) in manual precharge.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
t
WR = 10ns.
t
Notes
WR = 1
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