MT48LC2M32B2TG-6 :G Micron, MT48LC2M32B2TG-6 :G Datasheet - Page 52
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MT48LC2M32B2TG-6 :G
Manufacturer Part Number
MT48LC2M32B2TG-6 :G
Description
DRAM Chip SDRAM 64M-Bit 3.3V 86-Pin TSOP-II
Manufacturer
Micron
Datasheet
1.MT48LC2M32B2B5-7G.pdf
(69 pages)
- Current page: 52 of 69
- Download datasheet (3Mb)
Figure 34:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Power-Down Mode
COMMAND
Precharge all
BA0, BA1
DQM 0-3
active banks
A0-A9
CLK
CKE
A10
DQ
Note:
High-Z
t CKS
t CMS
t AS
SINGLE BANK
PRECHARGE
ALL BANKS
BANK(S)
T0
t CMH
t CKH
t AH
Violating refresh requirements during power-down may result in a loss of data.
Two clock cycles
All banks idle, enter
power-down mode
t CK
T1
NOP
t CKS
t CL
T2
NOP
Input buffers gated off while in
power-down mode
t CH
52
Exit power-down mode
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
t CKS
Tn + 1
NOP
All banks idle
©2001 Micron Technology, Inc. All rights reserved.
Tn + 2
ACTIVE
ROW
ROW
BANK
64Mb: x32 SDRAM
DON’T CARE
UNDEFINED
Timing Diagrams
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