MT48LC2M32B2TG-6 :G Micron, MT48LC2M32B2TG-6 :G Datasheet - Page 37
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MT48LC2M32B2TG-6 :G
Manufacturer Part Number
MT48LC2M32B2TG-6 :G
Description
DRAM Chip SDRAM 64M-Bit 3.3V 86-Pin TSOP-II
Manufacturer
Micron
Datasheet
1.MT48LC2M32B2B5-7G.pdf
(69 pages)
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Figure 28:
Figure 29:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Internal
States
Internal
States
READ with Auto Precharge Interrupted by a WRITE
WRITE with Auto Precharge Interrupted by a READ
Notes:
COMMAND
COMMAND
ADDRESS
Note:
ADDRESS
BANK m
BANK m
BANK n
BANK n
DQM
CLK
CLK
DQ
1. DQM is HIGH at T2 to prevent D
DQ
1
Active
Page
DQM is LOW.
READ - AP
BANK n,
Page Active
BANK n
COL a
T0
NOP
T0
READ with Burst of 4
WRITE - AP
BANK n,
Page Active
BANK n
Page Active
COL a
T1
D
T1
NOP
CL = 3 (BANK n)
a
IN
WRITE with Burst of 4
a + 1
T2
T2
D
NOP
NOP
IN
37
BANK m,
READ - AP
T3
COL d
T3
BANK m
OUT
D
NOP
OUT
a
Interrupt Burst, Write-Back
t
WR - BANK n
READ with Burst of 4
a + 1 from contending with D
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK m,
WRITE - AP
COL d
T4
BANK m
CL = 3 (BANK m)
T4
NOP
D
d
IN
Interrupt Burst, Precharge
WRITE with Burst of 4
T5
T5
d + 1
NOP
NOP
D
Precharge
IN
t
RP - BANK n
t
RP - BANK n
T6
T6
d + 2
D
NOP
NOP
D
OUT
d
IN
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
IN
DON’T CARE
DON’T CARE
d at T4.
T7
T7
t WR - BANK m
D
d + 1
d + 3
NOP
NOP
D
t RP - BANK m
OUT
IN
Write-Back
Idle
Commands
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