S9S12G96F0MLH Freescale Semiconductor, S9S12G96F0MLH Datasheet - Page 158
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S9S12G96F0MLH
Manufacturer Part Number
S9S12G96F0MLH
Description
16-bit Microcontrollers - MCU 16BIT 96K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G96F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
96 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G96F0MLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Port Integration Module (S12GPIMV1)
2.2.1
The availability of pins and the related peripheral signals are determined by a package code
(Section 2.4.3.33, “Package Code Register
programmed non-volatile memory location into the register during the reset sequence.
Based on the package code all non-bonded pins will have the input buffer disabled to avoid shoot-through
current resulting in excess current in stop mode.
2.2.2
If more than one output signal is attempted to be enabled on a specific pin, a priority scheme determines
the signal taking effect.
General rules:
Input signals are not prioritized. Therefore the input function remains active (for example timer input
capture) even if a pin is used with the output signal of another peripheral or general-purpose output.
2.2.3
Table 2-4
A signal name in squared brackets denotes the port register bit related to the digital I/O function of the pin
(port register PORT/PT not listed). It is a representative for any other port related register bit with the same
160
•
•
•
The peripheral with the highest amount of pins has priority on the related pins when it is enabled.
If a peripheral can selectively disable a function, the freed up pin is used with the next enabled
peripheral signal.
The general-purpose output function takes control if no peripheral function is enabled.
shows all pins with their related signals per device and package that are controlled by the PIM.
Package Code
Prioritization
Signals and Priorities
Table 2-3. Port Pin Availability (in largest package) per Device
Port
AD
M
C
D
E
T
S
P
J
MC9S12G Family Reference Manual,
(100 pin)
15-0
G1
7-0
7-0
1-0
7-0
7-0
3-0
7-0
7-0
(PKGCR)”). The related value is loaded from a factory
Device Group
(64 pin)
15-0
1-0
7-0
7-0
3-0
7-0
7-0
G2
-
-
Rev.1.23
(48 pin)
11-0
1-0
5-0
7-0
1-0
5-0
3-0
G3
-
-
Freescale Semiconductor
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