S9S12G96F0MLH Freescale Semiconductor, S9S12G96F0MLH Datasheet - Page 768
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S9S12G96F0MLH
Manufacturer Part Number
S9S12G96F0MLH
Description
16-bit Microcontrollers - MCU 16BIT 96K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G96F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
96 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G96F0MLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Timer Module (TIM16B8CV3)
23.3.2.17 Pulse Accumulators Count Registers (PACNT)
1
Read: Anytime
Write: Anytime
These registers contain the number of active input edges on its input pin since the last reset.
When PACNT overflows from 0xFFFF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set.
Full count register access should take place in one clock cycle. A separate read/write for high byte and low
byte will give a different result than accessing them as a word.
770
Module Base + 0x0022
Module Base + 0x0023
.
PAOVF
Reset
Reset
Field
PAIF
1
0
W
W
R
R
PACNT15
PACNT7
Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000.
Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of
PACTL register is set to one.
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the IOC7 input pin triggers PAIF.
Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of
PACTL register is set to one. Any access to the PACNT register will clear all the flags in this register when TFFCA
bit in register TSCR(0x0006) is set.
15
0
0
7
Readingthepulseaccumulatorcounterregistersimmediatelyafteranactiveedgeonthe
pulse accumulator input p in may miss the last c ount b ecause the input h as to be synchronized
with the bus clock first.
Figure 23-26. Pulse Accumulator Count Register High (PACNTH)
Figure 23-27. Pulse Accumulator Count Register Low (PACNTL)
PACNT14
PACNT6
14
0
0
6
MC9S12G Family Reference Manual,
Table 23-21. PAFLG Field Descriptions
PACNT13
PACNT5
13
0
0
5
PACNT12
PACNT4
NOTE
12
0
0
4
Description
PACNT11
PACNT3
11
0
0
3
Rev.1.23
PACNT10
PACNT2
10
0
0
2
PACNT9
PACNT1
Freescale Semiconductor
0
0
9
1
PACNT8
PACNT0
0
0
0
0
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