S9S12G96F0MLH Freescale Semiconductor, S9S12G96F0MLH Datasheet - Page 764
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S9S12G96F0MLH
Manufacturer Part Number
S9S12G96F0MLH
Description
16-bit Microcontrollers - MCU 16BIT 96K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G96F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
96 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G96F0MLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Timer Module (TIM16B8CV3)
23.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
23.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one while TEN bit of TSCR1 or PAEN bit of PACTL is set to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
766
Module Base + 0x000E
Module Base + 0x000F
C[7:0]F
Reset
Reset
Field
7:0
W
W
R
R
Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN or PAEN is set to
one.
Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
TOF
C7F
0
0
7
7
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
channel (0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
Unimplemented or Reserved
C6F
0
0
0
6
6
Figure 23-20. Main Timer Interrupt Flag 1 (TFLG1)
Figure 23-21. Main Timer Interrupt Flag 2 (TFLG2)
MC9S12G Family Reference Manual,
Table 23-16. TRLG1 Field Descriptions
C5F
0
0
0
5
5
C4F
NOTE
0
0
0
4
4
Description
C3F
0
0
0
3
3
Rev.1.23
C2F
0
0
0
2
2
Freescale Semiconductor
C1F
0
0
0
1
1
C0F
0
0
0
0
0
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