MAX1267BEEG Maxim Integrated, MAX1267BEEG Datasheet - Page 10

• Manufacturer Part Number: MAX1267BEEG
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1267BEEG

• Number Of Channels: 2/1
• Architecture: SAR
• Conversion Rate: 265 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: Yes
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 2.5 V or External

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Table 2. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
of the conversion cycle to restore node 0 to 0V within
the limits of 12-bit resolution. This action is equivalent to
transferring a 12pF (V
the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
Internal protection diodes, which clamp the analog
input to V
swing within (GND - 300mV) to (V
damage. However, for accurate conversions near full
scale, both inputs must not exceed (V
less than (GND - 50mV).
If an analog input voltage exceeds the supplies by
more than 50mV, limit the forward-bias input current to
4mA.
The MAX1265/MAX1267 T/H stage enters its tracking
mode on WR’s rising edge. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that, in internal clock
mode, this is approximately 1µs after writing the control
byte.
10
Table 3. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
*Channels CH2–CH5 apply to MAX1265 only.
*Channels CH2–CH5 apply to MAX1265 only.
A2
______________________________________________________________________________________
A2
0
0
0
0
1
1
0
0
0
0
1
1
DD
and GND, allow each input channel to
A1
0
0
1
1
0
0
A1
0
0
1
1
0
0
IN+
Analog Input Protection
- V
A0
0
1
0
1
0
1
IN-
A0
) charge from C
0
1
0
1
0
1
DD
DD
+ 300mV) without
CH0
+
+ 50mV) or be
Track/Hold
CH0
+
-
HOLD
CH1
+
to
CH1
+
-
In single-ended operation, IN- is connected to COM
and the converter samples the positive (+) input. In
pseudo-differential operation, IN- connects to the nega-
tive (-) input, and the difference of
pled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
t
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
where R
R
the input capacitance of the ADC. Source impedances
below 3kΩ have no significant impact on the MAX1265/
MAX1267s’ AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
ACQ
CH2*
IN
+
(800Ω) is the input resistance, and C
, is the maximum time the device takes to acquire
CH2*
S
+
-
is the source impedance of the input signal,
CH3*
+
t
ACQ
CH3*
= 9(R
+
-
CH4*
+
S
+ R
IN
CH4*
|
)C
(IN+) - (IN-)
+
-
CH5*
IN
+
IN
(12pF) is
CH5*
|
COM
is sam-
+
-
-
-
-
-
-
-