MAX1267BEEG Maxim Integrated, MAX1267BEEG Datasheet - Page 13

• Manufacturer Part Number: MAX1267BEEG
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1267BEEG

• Number Of Channels: 2/1
• Architecture: SAR
• Conversion Rate: 265 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: Yes
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 2.5 V or External

Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
To select the external clock mode, bits D6 and D7 of
the control byte must be set to 1. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an
external clock. For proper operation, a 100kHz to
4.8MHz clock frequency with 30% to 70% duty cycle is
recommended. Operating the MAX1265/MAX1267 with
CLK
CLK
WR
WR
CLK
CLK
WR
WR
ACQMOD = 1
ACQMOD = 1
with +2.5V Reference and Parallel Interface
t
CWH
______________________________________________________________________________________
ACQMOD = 0
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
t
CWS
ACQUISITION STARTS
ACQMOD = 0
ACQUISITION STARTS
t
t
DH
DH
ACQUISITION STARTS
External Clock Mode
ACQUISITION STARTS
t
CH
WR GOES HIGH WHEN CLK IS HIGH
WR GOES HIGH WHEN CLK IS LOW
t
CP
t
CL
WR GOES HIGH WHEN CLK IS HIGH.
WR GOES HIGH WHEN CLK IS LOW.
ACQUISITION ENDS
ACQUISITION ENDS
clock frequencies lower than 100kHz is not recommend-
ed, because the resulting voltage droop across the hold
capacitor in the T/H stage degrades performance.
The input and output data are multiplexed on a tri-state
parallel interface (I/O) that can easily be interfaced with
standard µPs. The signals CS, WR, and RD control the
write and read operations. CS represents the chip-
ACQUISITION ENDS
t
CWH
ACQUISITION ENDS
ACQMOD = 0
CONVERSION STARTS
CONVERSION STARTS
ACQMOD = 0
t
CWS
CONVERSION STARTS
CONVERSION STARTS
Digital Interface
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