MAX1267BEEG Maxim Integrated, MAX1267BEEG Datasheet - Page 4

• Manufacturer Part Number: MAX1267BEEG
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1267BEEG

• Number Of Channels: 2/1
• Architecture: SAR
• Conversion Rate: 265 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: Yes
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 2.5 V or External

TIMING CHARACTERISTICS
(V
T
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
4
Note 1: Tested at V
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to V
Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
Figure 1. Load Circuits for Enable/Disable Times
A
CLK Period
CLK Pulse Width High
CLK Pulse Width Low
Data Valid to WR Rise Time
WR Rise to Data Valid Hold Time
WR to CLK Fall Setup Time
CLK Fall to WR Hold Time
CS to CLK or WR Setup Time
CLK or WR to CS Hold Time
CS Pulse Width
WR Pulse Width
CS Rise to Output Disable
RD Rise to Output Disable
RD Fall to Output Data Valid
RD Fall to INT High Delay
CS Fall to Output Data Valid
DD
DOUT
= T
a) HIGH-Z TO V
_______________________________________________________________________________________
= +2.7V to +3.6V, COM = GND, REFADJ = V
MIN
6kΩ
been removed.
PARAMETER
to T
MAX
OH
AND V
, unless otherwise noted. Typical values are at T
DD
OL
TO V
= +3V, COM = GND, unipolar single-ended input mode.
C
20pF
LOAD
OH
SYMBOL
b) HIGH-Z TO V
DOUT
t
t
t
CSWH
t
CSWS
t
t
CWS
CWH
t
t
t
t
INT1
DO2
t
t
t
t
t
t
WR
CH
DH
DO
CP
CL
DS
CS
TC
TR
V
(Note 8)
C
C
C
C
C
DD
OL
LOAD
LOAD
LOAD
LOAD
LOAD
AND V
3kΩ
C
20pF
LOAD
DD
OH
, V
= 20pF, Figure 1
= 20pF, Figure 1
= 20pF, Figure 1
= 20pF, Figure 1
= 20pF, Figure 1
TO V
REF
OL
= +2.5V, 4.7µF capacitor at REF pin, f
CONDITIONS
A
= +25°C.)
MIN
208
100
40
40
40
40
40
60
60
20
20
20
0
0
CLK
= 4.8MHz (50% duty cycle),
TYP
DD
MAX
100
100
110
70
70
.
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns