MAX1267BEEG Maxim Integrated, MAX1267BEEG Datasheet - Page 9

• Manufacturer Part Number: MAX1267BEEG
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1267BEEG

• Number Of Channels: 2/1
• Architecture: SAR
• Conversion Rate: 265 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: Yes
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 2.5 V or External

Figure 3a. MAX1265 Simplified Input Structure
Table 1. Control-Byte Functional Description
the analog inputs. This configuration is pseudo-differ-
ential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
D2, D1, D0
D7, D6
BIT
SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
D5
D4
D3
COM
CH0
CH1
CH2
CH3
CH4
CH5
V
REF
with +2.5V Reference and Parallel Interface
INPUT
ACQMOD
MUX
PD1, PD0
SGL/DIF
UNI/BIP
A2, A1, A0
NAME
12-BIT CAPACITIVE DAC
C
CH0/CH1, CH2/CH3, AND CH4/CH5
_______________________________________________________________________________________
SWITCH
–
C
12pF
HOLD
TRACK
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
SWITCH
+
T/H
PD1 and PD0 select the various clock and power-down modes.
ACQMOD = 0: Internal acquisition mode
ACQMOD = 1: External acquisition mode
SGL/DIF = 0: Pseudo-differential analog input mode
SGL/DIF = 1: Single-ended analog input mode
In single-ended mode, input signals are referred to COM. In differential mode, the voltage difference
between two channels is measured (Tables 2 and 4).
UNI/BIP = 0: Bipolar mode
UNI/BIP = 1: Unipolar mode
In unipolar mode, an analog input signal from 0V to V
signal can range from -V
Address bits A2, A1, A0 select which of the 6/2 (MAX1265/MAX1267) channels are to be converted
(Tables 2 and 3).
R
800Ω
0
0
1
1
IN
HOLD
ZERO
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
0
1
0
1
COMPARATOR
Full power-down mode. Clock mode is unaffected.
Standby power-down mode. Clock mode is unaffected.
Normal operation mode. Internal clock mode selected.
Normal operation mode. External clock mode selected.
HOLD
REF
. At the
/2 to +V
FUNCTIONAL DESCRIPTION
REF
end of the acquisition interval, the T/H switch opens,
retaining charge on C
at IN+.
The conversion interval begins with the input multiplex-
er switching C
negative input (IN-). This unbalances node zero at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder
Figure 3b. MAX1267 Simplified Input Structure
/2.
SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR
COM
CH0
CH1
V
REF
REF
INPUT
HOLD
MUX
can be converted; in bipolar mode, the
12-BIT CAPACITIVE DAC
C
CH0/CH1
SWITCH
–
12pF
from the positive input (IN+) to the
C
HOLD
TRACK
HOLD
SWITCH
+
T/H
R
800Ω
IN
as a sample of the signal
HOLD
ZERO
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
COMPARATOR
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