S9S12GN16F0VLF Freescale Semiconductor, S9S12GN16F0VLF Datasheet - Page 373
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S9S12GN16F0VLF
Manufacturer Part Number
S9S12GN16F0VLF
Description
16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GN16F0VLF
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
16 KB
Data Ram Size
1024 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
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10.3.2.3
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
Read: Anytime
Write: Anytime if PLLSEL=1. Else write has no effect.
10.3.2.4
This register provides S12CPMU status bits and flags.
Read: Anytime
Write: Refer to each bit for individual write conditions
Freescale Semiconductor
1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by System Reset. Cleared by power on reset.
0x0036
0x0037
Reset
Reset
If PLL is selected (PLLSEL=1)
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
W
W
R
R
RTIF
S12CPMU Post Divider Register (CPMUPOSTDIV)
S12CPMU Flags Register (CPMUFLG)
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 10-6. S12CPMU Post Divider Register (CPMUPOSTDIV)
Note 1
PORF
0
0
6
6
Figure 10-7. S12CPMU Flags Register (CPMUFLG)
MC9S12G Family Reference Manual, Rev.1.23
f PLL
f bus
f PLL
Note 2
LVRF
0
0
5
5
=
=
=
f PLL
------------ -
---------------------------------------- -
(
f VCO
---------------
POSTDIV
2
4
f VCO
LOCKIF
0
0
4
4
+
1
)
S12 Clock, Reset and Power Management Unit (S12CPMU)
LOCK
0
0
3
3
POSTDIV[4:0]
Note 3
ILAF
0
2
2
OSCIF
1
0
1
1
UPOSC
1
0
0
0
375
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